Light emission delay circuit
First Claim
1. A light emission delay circuit for a timing light for adjusting the emission of light resulting from an ignition signal to a time when a piston in an engine cylinder reaches a top dead center position, comprising:
- (a) first means responsive to a first signal indicative of the time for the ignition of a particular engine cylinder and a second signal having a leading edge substantially indicating the ignition time of each engine cylinder for producing a third signal having a leading edge aligned with a leading edge of said second signal, said third signal being substantially two periods of said second signal beyond said first signal and having a pulse width equal to the period of said second signal;
(b) second means for delaying said leading edge of said third signal;
(c) third means for generating a fourth signal having a leading edge aligned with the leading edge of said third signal as delayed by said second means and a trailing edge aligned with a trailing edge of said third signal as supplied from said first means; and
(d) fourth means for counting a clock signal upwardly during the interval of said forth signal and then counting said clock signal downwardly during an interval equal to said interval of said fourth signal to produce an output signal for enabling the timing light to emit light.
1 Assignment
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Accused Products
Abstract
A light emission delay circuit adjusts a light emission time of a timing light into conformity with a time when a piston in an engine cylinder reaches a top dead center in detecting an ignition time for the engine cylinder. The light emission delay circuit comprises first means responsive to a first signal indicative of the ignition timing for the engine cylinder and a second signal having a leading edge substantially agreeing with the ignition time of the engine cylinder for producing a third signal having a leading edge with a leading edge of the second signal. The third signal is produced substantially two periods beyond the ignition time of the first signal, and also has a width of time equal to the period of the second signal. Second means for delaying the leading edge of the third signal, third means for generating a fourth signal having a leading edge aligned with the leading edge of the third signal as delayed by the second means and a trailing edge aligned with a trailing edge of the third signal as supplied from the first means, and fourth means for counting a clock signal upwardly during the interval of the fourth signal and then counting the clock signal downwardly during an interval equal to the interval of the fourth signal to produce an output signal for enabling the timing light to emit light are also provided.
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Citations
5 Claims
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1. A light emission delay circuit for a timing light for adjusting the emission of light resulting from an ignition signal to a time when a piston in an engine cylinder reaches a top dead center position, comprising:
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(a) first means responsive to a first signal indicative of the time for the ignition of a particular engine cylinder and a second signal having a leading edge substantially indicating the ignition time of each engine cylinder for producing a third signal having a leading edge aligned with a leading edge of said second signal, said third signal being substantially two periods of said second signal beyond said first signal and having a pulse width equal to the period of said second signal; (b) second means for delaying said leading edge of said third signal; (c) third means for generating a fourth signal having a leading edge aligned with the leading edge of said third signal as delayed by said second means and a trailing edge aligned with a trailing edge of said third signal as supplied from said first means; and (d) fourth means for counting a clock signal upwardly during the interval of said forth signal and then counting said clock signal downwardly during an interval equal to said interval of said fourth signal to produce an output signal for enabling the timing light to emit light. - View Dependent Claims (2, 3, 4, 5)
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Specification