Interface system for bus line control

• US 4,454,591 A
• Filed: 05/29/1980
• Issued: 06/12/1984
• Est. Priority Date: 05/29/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lou, Perry W.
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/154,560
• Time in Patent Office: 1,475 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/305
• CPC Class Codes: G06F 12/063 for I/O modules, e.g. memory mapped I/O I/O protocol G06F13/42
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An external I/O pull down latch and a system embodiment thereof. The interface system has a bus line including of a first means for providing an output at a fixed voltage level on said bus line for a first time interval, and a second means coupled to said bus line for maintaining the bus line at the fixed voltage level subsequent to the first time interval. In the preferred embodiment, the second means is comprised of said external I/O pull down latch. The present invention is a replacement for traditional pull up or pull down resistors in controlling I/O bus lines coupling main processor circuits with external memory circuits. In the preferred embodiment, the external I/O pull down latch is comprised of a read-write memory bit cell, sized such that it may be overdriven by any driver attached to the bus line.

Claims

1. An interface system comprising:

a bus means including at least one bus line;

at least one bus driver means for driving each of said bus lines to a selected one of two logic voltages thereby generating a predetermined logic state on said bus means when said bus driver means is actuated and for isolating each of said bus lines from each of said logic voltages by a high impedance when said bus driver means is inactivated; and

a default state latch means coupled to said bus means for continuously sensing the voltages on each of said bus lines and for automatically maintaining the last logic voltage on each bus line when all of said bus driver means are inactuated without external control, thereby preserving said predetermined logic state on said bus means.

2. An interface system as claimed in claim 1, wherein:

said default state latch includes a plurality of read/write memory cells, each read/write memory cell continuously coupled to a corresponding bus line.

3. An interface system as claimed in claim 2, wherein:

each of said read/write memory cells has means for continuously writing therein a logic state corresponding to said selected logic voltage on said corresponding bus line and means for reading out a logic voltage corresponding to said logic state written therein.

4. An interface system comprising:

a bus means including at least one bus line;

a first integrated circuit coupled to said bus means having (a) a bus driver means for driving each bus line to a selected one of two logic voltages thereby generating a predetermined logic state on said bus means when said bus driver means is actuated and for isolating each of said bus lines from each of said logic voltages by a high impedance when said bus driver means is inactuated, and (b) a default latch means for continuously sensing the voltages on each of said bus lines and for automatically maintaining the last logic voltage on each bus line when said bus driver means is inactuated without external control, thereby preserving said predetermined logic state on said bus means; and

at least one second integrated circuit coupled to said bus means having a bus responsive means for sensing the predetermined logic state of said bus means and generating a control signal corresponding to said sensed predetermined logic state.

5. An interface system as claimed in claim 4, wherein:

at least one of said second integrated circuits further includes a second bus driver means for driving each bus line to a selected one of two logic voltages thereby generating a predetermined logic state on said bus means when said second bus driver is actuated and for isolating each of said bus lines from each of said logic voltages by a high impedance when said second bus driver is inactuated.

6. An interface system as claimed in claim 4, wherein:

said default state latch includes a plurality of read/write memory cells, each read/write memory cell continuously coupled to a corresponding bus line.

7. An interface system as claimed in claim 6, wherein:

each of said read/write memory cells has means for continuously writing therein a logic state corresponding to said selected logic voltage on said corresponding bus line and means for reading out a logic voltage corresponding to said logic state written therein.

8. An interface system as claimed in claim 6, wherein:

each of said read/write memory cells includes a first pair of field effect devices having their gates connected in common to said corresponding bus line and having their source drain paths connected in series between a pair of voltage sources corresponding to said two logic voltages and a second pair of field effect devices having their gates connected in common to the junction of source drain paths between said first pair of field effect devices and having their source drain path connected in series between said pair of voltage sources.

9. An interface circuit comprising:

a bus coupling means for coupling to a bus having at least one bus line;

a bus driver means coupled to said bus coupling means for driving each of said bus lines to a selected one of two logic voltages thereby generating a predetermined logic state on said bus when said bus driver means is actuated and for isolating each bus line from each of said logic voltages by a high impedance when said bus driver means is inactuated; and

a default state latch means coupled to said bus coupling means for continuously sensing the voltages on each of said bus lines and for automatically maintaining the last logic voltage on each bus line when said bus driver is inactuated without, external control, thereby preserving said predetermined logic state on said bus.

10. An interface system as claimed in claim 9, wherein:

said default state latch includes a plurality of read/write memory cells, each read/write memory cell continuously coupled to a corresponding bus line.

11. An interface system as claimed in claim 10, wherein:

each of said read/write memory cells has means for continuously writing therein a logic state corresponding to said selected logic voltage on said corresponding bus line and means for reading out a logic voltage corresponding to said logic state written therein.