Digital data processing system having an I/O means using unique address providing and access priority control techniques

• US 4,455,602 A
• Filed: 05/22/1981
• Issued: 06/19/1984
• Est. Priority Date: 05/22/1981
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Haeffele, Steven M., Coder, William N., Baxter, Ward III
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/266,402
• Time in Patent Office: 1,124 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/5
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 9/35 Indirect addressing

Abstract

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

Claims

1. In a digital computer system including processor means for performing operations on operands, memory means for storing at least instructions for directing said operations, bus means for conducting said at least instructions between said memory means and said processor means, and I/O means connected to a selected one of said processor means or said memory means for conducting at least said operands between devices external to said digital computer system and said digital computer system, said I/O means comprising:

a plurality of data channel devices connected from said external devices and responsive to the operation of said external devices for conducting said operands between said external devices and said I/O means,

each of said data channel devices being connected from at least one of said external devices and having a compatible data transmission interface to said at least one of said external devices,

data mover means connected between each of said plurality of data channel devices and said selected means of said digital computer system for conducting said operands between said plurality of data channel devices and said selected means of said digital computer system, and

control means connected to said data channel devices, said external devices and said data mover means and responsive to the operation of said plurality of data channel devices and said digital computer system for providing control outputs for controlling the conducting of said operands between said external devices and said digital computer system, and

further wherein each of said plurality of data channel devices further comprises;

means for providing addresses of storage locations in said memory means to permit the conducting of said operands between said storage locations of such memory means and said at least one of said external devices,

said address providing means including map memory means for storing a map comprising said addresses,

and said control means further comprises means for providing a said map for each said map memory means of each of said plurality of data channel devices.

2. The digital computer system of claim 1, wherein each of said plurality of data channel devices further comprises:

buffer memory means for storing said operands being conducted between said selected means of said digital computer system and said at least one of said external devices.

3. The digital computer system of claims 1 or 2 wherein said data mover means further comprises:

ring generator means for providing a repetitive sequence of access available outputs representing sequential access periods in time to said selected means of said digital computer system,

gating means for associating at least a selected one of said access available outputs with each of said plurality of data channel devices,

said gating means being responsive to the operation of each of said plurality of data channel devices and to said access available outputs for providing grant control outputs to said data mover means and to each of said plurality of data channel devices for granting access to said selected means of said digital computer system to each of said plurality of data channel means upon coincidence of a requirement by one of said plurality of data channel means for access to said selected means of said digital computer system and an associated selected one of said access available outputs.

4. The digital computer system of claim 3 wherein said data mover means has a first port connected from each of said plurality of data channel devices and a second port connected from said selected means of said digital computer system for conducting said operands therebetween;

and

said first port has a data transmission interface compatible with each of said plurality of data channel devices and said second port has a data transmission interface compatible with said selected means of said digital computer system.

7. The digital computer system of claims 1, 2, 5 or 6 wherein said data mover means has a first port connected from each of said plurality of data channel devices and a second port connected from said selected means of said digital computer system for conducting said operands therebetween;

and

said first port has a data transmission interface compatible with each of said plurality of data channel devices and said second port has a data transmission interface compatible with said selected means of said digital computer system.

5. In a digital computer system including processor means for performing operations on operands, memory means for storing at least instructions for directing said operations, bus means for conducting said at least instructions between said memory means and said processor means, and I/O means connected to a selected one of said processor means or said memory means for conducting at least said operands between devices external to said digital computer system and said digital computer system, said I/O means comprising:

a plurality of data channel devices connected from said external devices and responsive to operation of said external devices for conducting said operands between said external devices and said I/O means,

each one of said data channel devices being connected from at least one of said external devices and having a compatible data transmission interface to said at least one of said external devices,

data mover means connected between each of said plurality of data channel devices and said selected means of said digital computer system for conducting said operands between said plurality of data channel devices and said selected means of said digital computer system, and

control means connected to said data channel devices, said external devices and said data mover means and responsive to the operation of said plurality of data channel devices and said digital computer system for providing control outputs for controlling the conducting of said operands between said external devices and said digital computer system

and further wherein said data mover means further comprises

ring generator means for providing a repetitive sequence of access available outputs representing sequential access periods in time to said selected means of said digital computer system,

gating means for associating at least a selected one of said access available outputs with each of said plurality of data channel devices,

said gating means responsive to operation of each of said plurality of data channel devices and to said access available outputs for providing grant control outputs to said data mover means and to each of said plurality of data channel devices for granting access to said selected means of said digital computer system to each of said plurality of data channel means upon coincidence of a requirement by one of said plurality of data channel means for access to said selected means of said digital computer system and an associated selected one of said access available outputs.

6. The digital computer system of claim 5, wherein each of said plurality of data channel devices further comprises buffer memory means for storing said operands being conducted between said selected means of said digital computer system and said at least one of said external devices.