Interactive equipment for computer programming by linkage of labeled block representations of arithmetic/logical subprograms

• US 4,455,619 A
• Filed: 05/29/1981
• Issued: 06/19/1984
• Est. Priority Date: 05/30/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Masui, Shoichi, Takaki, Masaoki, Yamanaka, Kunio, Oonari, Mikihiko
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Williams, Jr., Archie E.
• Application Number:
  US06/268,369
• Time in Patent Office: 1,117 Days
• Field of Search: 364/200, 364/900, 364/300, 364/147, 364/488, 364/491
• US Class Current: 345/530
• CPC Class Codes: G05B 19/056 Programming the PLC
• CPC Class Codes: G06F 3/0489 using dedicated keyboard keys or combinations thereof
• CPC Class Codes: G06F 3/04892 Arrangements for controlling cursor position based on codes indicative of cursor displacements from one discrete location to another, e.g. using cursor control keys associated to different directions or using the tab key arrangements for controlling cursor position based on coordinate signals G06F3/038
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A programming equipment is used for automatically constructing programs by selecting and interconnecting a plurality of previously prepared unit programs in accordance with instructions by an operator. A screen of a display unit is divided into a plurality of partial display areas. A memory has a plurality of unit storage areas, one for each partial display area, for storing unit program names and data flow specifications. The information of the respective area is displayed in block form on the display unit so that the operator can readily construct a process data flow by operating the input device while watching the display unit. The programming equipment reads out the area information from the areas in a predetermined sequence, and selects and interconnects the unit programs to construct the program corresponding to the process data flow.

Claims

1. A programming equipment comprising:

a display unit including means for displaying in each of a plurality of partial display areas on a display screen the symbol of a subprogram comprising a block diagram image and the name of a subprogram predetermined for each of a plurality of arithmetic and logical operations with a data flow indicating symbol between block diagram symbols to indicate the path of data flow between subprograms;

memory means having a plurality of unit memory areas, one for each of said plurality of partial display areas of said display unit, for storing data relating to selected subprograms and having an address memory area for storing address information to designate one of said plurality of unit memory areas;

an input including means for inputting names of subprograms, data flow specifications for specifying symbols indicating the data flows between said subprograms, instructions for modifying said address information stored in the address memory area of said memory means and instructions for reading out data from said plurality of unit memory areas of said memory means to an external program utilization unit; and

processor means connected to said display unit, said input device and said memory means for storing the names of subprograms and said data flow specifications received from said input device into the unit memory areas of said memory means designated by said address information stored in said address memory area of said memory means and for controlling said display unit to display the symbols and names of said subprograms and the data flows specified by said data flow specifications as stored in said memory means in the partial display areas on the screen of said display unit designated by said address information, including means for reading out the names of said subprograms and said data flow specifications from said plurality of unit memory areas in a predetermined sequence to said external program utilization unit.

2. A programming equipment according to claim 1 wherein said memory means includes a subprogram memory area having a plurality of subprograms stored therein and flag information areas, one for each of said plurality of subprograms, and said processor means includes means for setting the flag information area corresponding to the name of a subprogram received from said input device and for reading out from the subprogram memory area the subprogram corresponding to the flag information area set by said processor in response to the read-out instructions from said input device.

3. A programming equipment according to claim 2 wherein said display unit includes frame memory means for storing a frame of video information to be displayed on said display screen and display controller means connected to said processor means for storing in said frame memory means video information corresponding to the symbols and names of the subprograms and the data flows specified by said data flow specifications as stored in said memory means.

4. A programming equipment according to claim 3, further including a control processor connected to said processor means for controlling said external program utilization unit and including external memory means for storing a series of subprograms in successive storage locations to form a program for control of said external program utilization unit by said control processor.

5. A programming equipment according to claim 4 wherein said memory means includes a buffer memory area for storing an address of said external memory means representing a beginning address for storing a subprogram therein, and wherein said processor means includes means for transferring subprograms from said subprogram memory area of said memory means to said external memory means for storage beginning at the address stored in said buffer memory area in response to said read-out instruction from said input device and in accordance with the names of the subprograms stored in the unit memory areas of said memory means.

6. A programming equipment according to claim 5 wherein said memory means includes a subprogram memory capacity area for storing the memory capacity required for each subprogram in said subprogram memory area, and wherein said processor means includes means for increasing the value of the address stored in said buffer memory area by the amount of the memory capacity of a subprogram transferred to said external memory means in accordance with the information stored in said subprogram memory capacity area for that subprogram at each time of transfer of a subprogram to said external memory means so that each subprogram is stored in said external memory means immediately adjacent to the previous subprogram transferred thereto.