Test apparatus for electronic assemblies employing a microprocessor

• US 4,455,654 A
• Filed: 06/05/1981
• Issued: 06/19/1984
• Est. Priority Date: 06/05/1981
• Status: Expired due to Fees

• Current Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Original Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Inventors: Carlson, Alden J., Scott, Marshall H., Bhaskar, Kasi S., Couper, Alastair N., Lambert, Dennis L.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/270,926
• Time in Patent Office: 1,110 Days
• Field of Search: 371/20, 371/25, 371/29, 324/73 R, 324/73 AT
• US Class Current: 714/28
• CPC Class Codes: G01R 19/16557 Logic probes, i.e. circuits indicating logic state (high, low, O); modifications of electronic switches or gates for indicating state of switch H03K17/18
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/2257 using expert systems
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 11/32 with visual or acoustical indication of the functioning of the machine
• CPC Class Codes: G06F 11/325 by lamps or LED's

Abstract

A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

Claims

1. A test system for functionally testing a microprocessor-based assembly of the type wherein a microprocessor circuit communicates with at least one of a random access memory unit, a read-only memory unit and an input/output register via an interconnection bus, and a clock circuit coupling a periodic clock signal to said microprocessor circuit to establish a bus cycle of a predetermined length, said test system comprising:

a second microprocessor circuit substantially identical to said microprocessor circuit of said microprocessor-based assembly being tested;

interconnection means for connecting said test system to said microprocessor-based assembly being tested with said test system being connected to replace said microprocessor circuit of said assembly being tested, said interconnection means including means for coupling said clock signal to said second microprocessor circuit;

memory means, including means for storing instructions and data for programming said second microprocessor circuit, for supplying addressing and data signals;

switching means for selectively coupling said second microprocessor circuit between a first operational state wherein said second microprocessor is in signal communication with said memory means and a second operational state wherein said second microprocessor circuit is in signal communication with said interconnection means to supply signals to and receive signals from said interconnection bus of said microprocessor-based assembly being tested, said switching means including timing means responsive to said clock signal supplied by said microprocessor-based assembly for switching said second microprocessor circuit into said second operational state at a predetermined time, said second microprocessor circuit being maintained in said second operational state for a single bus cycle each time said switching means switches said second microprocessor from said first operational state to said second operational state.

2. The apparatus as claimed in claim 1 including register means connected to said interconnection means, said register means being responsive to an applied register control signal for storing a signal appearing on said interconnection means at the time said register control signal is supplied to said register means, said switching means including means for supplying said register control signal to said register each time said second microprocessor circuit is switched to said second operational state.

3. The apparatus as claimed in claim 2 wherein register means is also responsive to a second applied register control signal to permit stored signals to be read from said register means by said second microprocessor circuit and said switching means includes means for supplying said second register control signal when said second microprocessor circuit is in said first operational state.

4. The apparatus as claimed in claim 3 wherein said timing means is responsive to an applied timing signal and includes means for switching said second microprocessor circuit into said second operational state after the elapse of a predetermined number of clock periods of said clock signal supplied by said microprocessor-based assembly being tested and said memory means includes instructions and data for sequencing said second microprocessor circuit to supply said timing signal to said timing means.

5. The apparatus as claimed in claim 4 wherein said second microprocessor circuit, said memory means, said register means and said switching means are located in an interface unit that further includes an input/output unit connected in data communication with said second microprocessor circuit;

said test system further includes a mainframe assembly that includes a programmable microprocessor system connected in data communication with said input/output unit of said interface unit, said mainframe assembly including data entry means, display means and mainframe memory means collectively configured and interconnected for transmitting data signals to said interface unit for initiating an operational sequence by said second microprocessor circuit that includes at least one transition from said first state to said second state.

6. The apparatus as claimed in claims 1, 3, or 5 including address signal means connected to said interconnection means and arranged for coupling a predetermined address signal to said interconnection bus of said microprocessor-based assembly whenever said second microprocessor circuit is in said first state.

7. The apparatus as claimed in claims 1, 3, or 5 including a probe unit for monitoring logic signal conditions at a selected circuit node of said microprocessor-based assembly being tested, said probe unit including means for supplying a first indication of a first predetermined time duration each time the monitored signal attains a first predetermined level and means for supplying second indication for a period of time that is substantially equal to said first predetermined time duration each time said monitored signal is less than a second predetermined level, said probe unit further including means for disabling said means for supplying said first indication and said means for supplying said second indication for a period of time that is less than said first predetermined time duration each time said monitored signal remains between said first and second predetermined levels for a period of time that is greater than a second predetermined time duration.

8. The apparatus as claimed in claim 7 wherein said means for supplying said first and second indication each include means for sampling the signal level at said monitored circuit node in substantial time coincidence with an applied sync signal and said test system includes means for supplying a sync signal to said means for sampling said signal level each time said second microprocessor is switched to said second operational state.

9. The apparatus as claimed in claim 7 wherein said probe unit further includes signal source means selectively operable to supply of first signal pulse that exceeds said first predetermined level and a second signal pulse that is less than said second predetermined level, the probe unit signal source means also being selectively operable to supply an alternating sequence of said first and second signal pulses.

10. The apparatus as claimed in claim 9 wherein said signal source means supplies each one of said first signal pulses, each one of said second signal pulses and each individual pulse of said alternating sequence of said first and second signal in substantial synchronism with an applied synch signal and said test system includes means for supplying a sync signal to said signal source means each time said second microprocessor circuit is switched to said second operational state.

11. The apparatus as claimed in claim 10 wherein said means for supplying said first and second indication includes means for sampling the signal level at said monitored node in substantial synchronism with said test system sync signal.

12. Apparatus for testing logic circuitry comprising:

a test probe, said test probe including an elctrode positionable in signal communication with a circuit node of logic circuitry being tested;

a first signal indicator for supplying a humanly perceivable signal and being responsive to an applied first control signal;

a second signal indicator for supplying a humanly perceivable signal and being responsive to an applied second control signal;

first signal detection means connected for receiving the signal supplied to said electrode and being connected for supplying said first control signal to said first signal indicator, said first signal detection means including means for supplying said first control signal for a predetermined time, T, each time said electrode supplies the signal of a first predetermined magnitude;

second signal detection means connected for receiving the signal supplied to said electrode and being connected for supplying said second control signal to said second signal indicator, said second signal detection means including means for supplying said second control signal for a predetermined time, T, each time said electrodes supplies a signal of a second predetermined magnitude;

third signal detection means connected for receiving the signal being supplied to said electrode, said third signal detection means including means for disabling said first and said second signal detection means for a period of time less than said predetermined time, T, each time said electrode supplies a signal having a magnitude between said first and second predetermined magnitudes.

13. The apparatus for testing logic circuitry as claimed in claim 12 including signal synchronization means responsive to an applied synchronization signal and including means for coupling said signal supplied by said elctrode to said first, second and third signal detection means in substantial time coincidence with said applied synchronization signal.

14. The apparatus for testing logic circuitry as claimed in claims 12 or 13 including:

a first pulse generator responsive to an applied first pulse control signal and including means for coupling a signal pulse of a first predetermined signal level to said electrode of said test probe;

a second pulse generator responsive to an applied second pulse control signal and including means for coupling a signal pulse of a second predetermined signal level to said electrode of said test probe; and

control means responsive to an applied signal selector signal, said control means including means for individually supplying said first and second pulse control signals to said first and second pulse generators, said control means further including means for supplying an alternating sequence of said first and second signal pulses to said first and second pulse generators.

15. Apparatus for determining a set of responses for a faultless processor controlled device comprising:

memory means containing a predetermined set of instructions;

interconnection means for connecting said apparatus to said processor controlled device; and

apparatus processor means connected to said memory means and said interconnection means and alternating between (1) a first operational state wherein said apparatus processor means is in communication with said memory means and isolated from said processor controlled device to selectively receive said predetermined set of instructions from said memory means and provide said set of responses obtained from said processor controlled device to said memory means and (2) a second operational state wherein said apparatus processor means is in communication with said processor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said processor controlled device and receive signals from said processor controlled device as said set of responses; and

means included in said memory means to retain said set of responses provided by said apparatus processor means as said set of responses for said faultless processor controlled device.

17. The apparatus as claimed in claim 15 or 16 wherein said apparatus processor means includes means responsive to sequential signals in said processor controlled device to change said apparatus processor means between said first and second operational states.

18. The apparatus as claimed in claim 15 or 16, wherein said processor controlled device includes dynamic circuit means, said apparatus including generator means connected to said interconnection means for providing periodic signals to continuously refresh said dynamic circuit means in said processor controlled device.

19. The apparatus as claimed in claim 15 or 16 including drivability sensing means connected to said interconnection means for determining if said predetermined signals provided by said apparatus processor means are provided by said interconnection means to said processor controlled device.

20. The apparatus as claimed in claim 15 or 16 including drivability means for determining which of said predetermined signals have been provided by said interconnection means to said processor controlled device.

21. The apparatus as claimed in claim 15 or 16 wherein said apparatus processor means includes means for selectively providing input signals to said processor controlled device and receiving signals therefrom when said apparatus processor means is in said second operational state.

22. The apparatus as claimed in claim 15 or 16 including power sensing means connected to said interconnection means responsive to the lack of said predetermined signals to provide an indication of the failure of a power supply in said processor controlled device.

23. The apparatus as claimed in claim 15 or 16 including limiting means connected to said interconnection means to limit the value of said predetermined signals and of said set of responses from said processor controlled device.

24. The apparatus as claimed in claim 15 or 16 including probe means operatively connected to said memory means to provide signals indicative of logic levels at selected locations in said processor controlled device.

25. The apparatus as claimed in claim 15 or 16 including probe means operativey connected to said memory means responsive to said predetermined set of instructions to provide signals indicative of logic levels at selected locations in said processor controlled device.

26. The apparatus as claimed in claim 15 or 16 including probe means operatively connected to said memory means for providing signal pulses to selected locations in said processor controlled device.

27. The apparatus as claimed in claim 15 or 16 including probe means operativey connected to said memory means and said apparatus processor means responsive to said apparatus processor means operating in said first or second state to selectively provide signals to selected locations in said processor controlled device in said first or second state or both.

28. The apparatus as claimed in claim 15 or 16 including probe means operatively connected to said memory means and including means operatively associated with said memory means and said probe means to cause said apparatus processor means to provide one of said predetermined signals for detection of said signal by said probe means at selected locations in said processor controlled device.

16. Apparatus for detecting faults in a processor controlled device comprising:

memory means containing a predetermined set of instructions and a predetermined set of responses;

interconnection means for connecting said apparatus to said processor controlled device; and

apparatus processor means connected to said memory means and said interconnection means and alternating between (1) a first operational state wherein said apparatus processor means is in communication with said memory means and isolated from said processor controlled device to selectively receive said predetermined set of instructions from said memory means and provide to said memory means a set of responses previously developed from said processor controlled device and (2) a second operational state wherein said apparatus processor means is in communication with said processor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said processor controlled device and receive signals from said processor controlled device as said set of responses, said apparatus processor means including means for processing said set of responses from said processor controlled device to develop said predetermined signals; and

means for detecting a fault when said predetermined set of responses differs from said set of responses from said processor controlled device.

29. Apparatus for determining a set of responses for a faultless microprocessor controlled device comprising:

memory means containing a predetermined set of instructions;

interconnection means for connecting said apparatus to said microprocessor controlled device;

an apparatus microprocessor pod connected to said memory means and said interconnection means operable alternately in (1) a first operational state wherein said apparatus microprocessor pod is in communication with said memory means and isolated from said microprocessor controlled device to selectively receive said predetermined set of instructions from said memory means and provide said set of responses to said memory means and (2) a second operational state wherein said apparatus microprocessor is in communication with said microprocessor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said microprocessor controlled device and receive signals from said microprocessor controlled device as said set of responses; and

recording means in said memory means to retain said set of responses as said set of responses for said faultless microprocessor controlled device.

31. The apparatus as claimed in claim 29 or 30 including switching means in said apparatus microprocessor pod responsive to clock signals from a clock in said microprocessor controlled device to change said apparatus microprocessor pod between said first and second operational states according to said predetermined set of instructions from said memory means.

32. The apparatus as claimed in claim 29 or 30, wherein said microprocessor controlled device includes dynamic circuit means, said apparatus including generator means in said microprocessor pod connected to said interconnection means for providing periodic signals for continuously refreshing said dynamic circuit means in said microprocessor controlled device.

33. The apparatus as claimed in claim 29 or 30 including drivability sensing means in said apparatus microprocessor pod connected to said interconnection means for determining which of said predetermined signals provided by said apparatus microprocessor pod are provided by said interconnection means to said microprocessor controlled device.

34. The apparatus as claimed in claim 29 or 30 including drivability means in said apparatus microprocessor pod for determining if all of said predetermined signals have been provided by said interconnection means to said microprocessor controlled device.

35. The apparatus as claimed in claim 29 or 30 wherein said apparatus processor pod includes means for selectively providing predetermined signals to said processor controlled device and receiving the response signals to said predetermined signals therefrom when said apparatus processor pod is in said second operational state.

36. The apparatus as claimed in claim 29 or 30 including power sensing means connected to said interconnection means responsive to the lack of said predetermined signals and clock signals from said microprocessor controlled device to provide an indication of the failure of a power supply in said microprocessor controlled device.

37. The apparatus as claimed in claim 29 or 30 including limiting resistor circuitry connected to said interconnection means to limit the value of said predetermined signals and of said set of responses from said microprocessor controlled device.

38. The apparatus as claimed in claim 29 or 30 including probe means connected to said memory means to provide visual signals indicative of logic levels at selected locations in said microprocessor controlled device.

39. The apparatus as claimed in claim 29 or 30 including probe means operatively connected to said memory means responsive to said predetermined set of instructions to provide signals indicative of logic levels at selected locations in said microprocessor controlled device.

40. The apparatus as claimed in claim 29 or 30 including probe means operatively connected to said memory means for providing signal pulses to selected locations in said microprocessor controlled device.

41. The apparatus as claimed in claim 29 or 30 including probe means operatively connected to said memory means and said apparatus processor pod responsive to said apparatus microprocessor pod operating in said first or second operational state to selectively provide signals to selected locations in said microprocessor controlled device in said first or second operational state or both.

42. The apparatus as claimed in claim 29 or 30 including probe means operatively connected to said memory means and including means operatively associated with said memory means and said probe means for said memory means to cause said apparatus microprocessor pod to provide one of said predetermined signals for detection of said signal by said probe means at one of said selected locations in said microprocessor controlled device.

30. Apparatus for detecting faults in a microprocessor controlled device comprising:

memory means containing a predetermined set of instructions and a predetermined set of responses;

interconnection means for connecting said apparatus to said microprocessor controlled device; and

an apparatus microprocessor pod connected to said memory means and said interconnection means, said apparatus microprocessor pod including an apparatus microprocessor alternating between (1) a first operational state in communication with said memory means, to selectively receive said predetermined set of instructions from said memory means and provide a set of responses to said memory means, and (2) a second operational state in communication with said microprocessor controlled device to selectively execute said set of instructions by providing predetermined signals to said microprocessor controlled device and receive signals therefrom as said set of responses; and

comparison means in said memory means for comparing said predetermined set of responses and said set of responses and providing a visual fault indication when said responses differ.

43. Apparatus for determining a memory map for a faultless microprocessor controlled device having a removeable microprocessor and an internal clock providing periodic clock signals, comprising:

main memory means containing predetermined sets of instructions and selectable to provide one of said predetermined sets of instructions;

interconnection means for connecting said apparatus to said microprocessor controlled device where said microprocessor has been removed;

pod memory means operatively connected to said interconnection means and said main memory means responsive to said one of said predetermined sets of instructions therefrom to provide a predetermined test sequence and set of stimulation signals;

a pod microprocessor connected to said pod memory means and said interconnection means sequentially operable in a first operational state to receive said predetermined test sequence and said set of stimulation signals from said pod memory means, operable in a second operational state to execute said predetermined test sequence and provide said set of stimulation signals to said microprocessor controlled device, operable in said second operational state to receive response signals due to said stimulation signals from said microprocessor controlled device and provide said response signals to said pod memory means, and operable in said first operational state to provide said response signals to said main memory means;

switching means responsive to said periodic clock signals for switching said pod microprocessor between said first and second operational states; and

main processor means connected to said main memory means responsive to said response signals to retain said response signals as a memory map for said faultless microprocessor controlled device.

45. The apparatus as claimed in claim 43 or 44 including means connected to said pod microprocessor and said main memory means responsive to said clock signals from said microprocessor controlled device switch said pod microprocessor between said first and second operational states according to said one of said predetermined sets of instructions.

46. The apparatus as claimed in claim 43 or 44 including a generator connected to said interconnection means for providing periodic signals for continuously refreshing dynamic circuit means in said microprocessor controlled device when said pod microprocessor is in said first operational state.

47. The apparatus as claimed in claim 43 or 44 including driveability sensing means connected to said interconnection means for determining which and how said predetermined signals provided by said main processor means is provided by said interconnection means to said microprocessor controlled device.

48. The apparatus as claimed in claim 43 or 44 including drivability means for determining if all of said prederermined signals have been provided by said interconnection means to said microprocessor controlled device and means in said drivability means providing an indication when said predetermined signals are not provided.

49. The apparatus as claimed in claim 43 or 44 including operator controllable means connected to said apparatus processor means for selectively providing a predetermined sequence of signals to and receiving response signals to said predetermined sequence signals from said microprocessor controlled device.

50. The apparatus as claimed in claim 43 or 44 including power sensing means connected to said interconnection means responsive to the lack of said predetermined signals and clock signals from said clock in said microprocessor controlled device to provide an indication of a failure of a power supply in said microprocessor controlled device.

51. The apparatus as claimed in claim 43 or 44 including resistor and diode means connected to said interconnection means to limit the value of said predetermined signals and said signals from said microprocessor controlled device and to stimulate the impedance of said removed microprocessor.

52. The apparatus as claimed in claim 43 or 44 including probe means operatively connected to said memory means to inject controlled duration signals indicative of a duality of logic levels at selected locations and said microprocessor controlled device when said pod microprocessor is operable in said second operational state, said probe means including means for sensing logic levels at said selected locations after injecting said signals.

53. The apparatus as claimed in claim 43 or 44 including probe means operatively connected to said main memory means and said main processor means responsive to said predetermined set of instructions to provide controlled duration signals indicative of logic levels at selected locations in said microprocessor controlled device when said pod microprocessor is operable in said second operational state, said probe means including means for sensing and indicating the presence of a plurality of logic levels at selected locations after injecting said signals.

54. The apparatus as claimed in claim 43 or 44 including probe means operatively connected to said main memory means for sensing and retaining indications of signals at selected locations in said microprocessor controlled device caused by said stimulation signals.

55. The apparatus as claimed in claim 43 or 44 including probe means operatively connected to said main memory means in said pod microprocessor responsive to said pod microprocessor operating in said first or second operational state to selectively provide signals to said selected locations in said microprocessor controlled device in said first or second operational state or both.

56. The apparatus as claimed in claim 43 or 44 including probe means operatively connected to said main memory means and including means operatively associated with said main memory means and said probe means for causing said pod microprocessor means to provide one of said predetermined signals for detection of said signal by said probe means at one of said selected locations in said microprocessor controlled device when said pod microprocessor is operable in said second operational state.

44. Apparatus for detecting faults in a microprocessor controlled device having a removable microprocessor and an internal clock providing periodic clock signals, comprising:

main memory means containing predetermined sets of instructions and a predetermined faultless map;

interconnection means for connecting said apparatus to said microprocessor controlled device where said microprocessor has been removed;

pod memory means operatively connected to said main memory means responsive to one of said predetermined sets of instructions therefrom to provide a predetermined test sequence and set of stimulation signals;

a pod microprocessor connected to said pod memory means and said interconnection means sequentially operable in a first operational state operatively connected to said pod memory means to receive said predetermined test sequence and set of stimulation signals, operable in a second operational state operatively connected to said microprocessor controlled device to execute said predetermined test sequence by providing said stimulation signals to said microprocessor controlled device, operable in said second operational state to receive response signals due to said stimulation signals from said microprocessor controlled device and to provide said response signals to said pod memory means, and operable in said first operational state to provide said response signals to said main memory means;

switching means responsive to said periodic clock signals for switching said pod microprocessor between said first and second operational states; and

main processor means connected to said main memory means responsive to said response signals to establish a device memory map for said microprocessor controlled device, said main processor means including means for comparing said predetermined faultless memory map with said device memory map to determine differences there between whereby faults may be detected.