Method of manufacturing a self-aligned U-MOS semiconductor device

• US 4,455,740 A
• Filed: 09/29/1982
• Issued: 06/26/1984
• Est. Priority Date: 12/07/1979
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Iwai, Hiroshi
• Primary Examiner(s): Massie, Jerome W.
• Application Number:
  US06/426,667
• Time in Patent Office: 636 Days
• Field of Search: 156/648, 156/649, 156/653, 156/657, 29/571, 29/578, 29/580, 29/591, 357/55, 357/23
• US Class Current: 438/270
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 148/02 Contacts, special
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/053 Field effect transistors fets
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

A method of manufacturing a MOS semiconductor device, which comprises a step of forming a groove in a predetermined portion of a semiconductor substrate, a step of forming a gate insulation film to cover the entire surface of the substrate inclusive of the groove, a step of depositing a gate electrode material to a thickness greater than one half the width of the opening of the groove to thereby fill the groove with the gate electrode material, and a step of forming a gate electrode within the groove by etching away the gate electrode material until the gate insulation film other than that within the groove is exposed. Before the step of etching the gate electrode material, a portion of the gate material layer including a portion thereof over part of the groove and/or a portion of the layer other than that within the groove may be covered with a mask material to simultaneously form a lead integral with the gate electrode within the groove and/or a separate gate electrode at the time of the etching of the gate electrode material.

Claims

1. In a method of manufacturing a gate electrode and source and drain regions in a portion of a semiconductor substrate between field oxide regions in a MOS semiconductor device, the improvement comprising the steps of:

(a) forming a groove substantially U-shaped in cross-section in a predetermined exposed portion of said semiconductor substrate where said gate electrode is to be located;

(b) forming a gate insulated film to cover the surface of said substrate inclusive of said groove;

(c) depositing a gate electrode material on said substrate to a thickness greater than one half the width of the opening of said groove to thereby fill said groove with said gate electrode material;

(d) forming a gate electrode by etching away said gate electrode material until said gate insulation film, except for a portion thereof within said groove, is exposed, thereby forming the gate electrode in a self-aligned manner, the gate electrode being substantially buried within the substrate such that the upper surface of the gate electrode is substantially even with or lower than the surface of the substrate surrounding the gate electrode; and

(e) forming source and drain regions between respective side portions of the field oxide regions and respective side portions of said groove filled with said gate material by diffusing an impurity utilizing said groove filled with said gate electrode material and said field oxide regions as masks to thereby form self-aligned source and drain regions substantially only within the substrate.

2. The method of claim 1 wherein said step of forming a self-aligned gate electrode includes covering a portion of said gate electrode material, inclusive of a part thereof over part of said groove, with a mask material followed by said etching away of said gate electrode material until said gate insulation film, except for portions thereof beneath said mask material and over said groove, is exposed to thereby obtain a self-aligned gate electrode within said groove and a lead integral to said gate electrode.

9. The method according to claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein said etching in said step of forming is continued until the surface of said self-aligned gate electrode is slightly depressed with respect to the open top of said groove.

10. The method according to claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein said step of forming a groove includes the formation of two or more grooves having different depths.

11. The method according to claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein said step of forming a groove is followed by a step of implantation of an impurity in said groove to control the threshold voltage of said semiconductor device.

12. The method of claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein said step of forming a groove includes formation of a groove having a depth greater than the width of said groove.

3. In a method of manufacturing both a self-aligned gate electrode and a non-self-aligned gate electrode and respective source and drain regions located in a portion of semiconductor substrate between field oxide regions in a MOS semiconductor device, the improvement comprising the steps of:

(a) forming a groove substantially U-shaped in cross-section in a predetermined exposed portion of said semiconductor substrate where said self-aligned gate electrode is to be located;

(b) forming a gate insulation film to cover the surface of said substrate inclusive of said groove;

(c) depositing a gate electrode material on said substrate to a thickness greater than one half the width of the opening of said groove to thereby fill said groove with said gate electrode material;

(d) simultaneously forming both a self-aligned gate electrode and a non-self-aligned gate electrode by (i) covering a first portion of said gate electrode material remote from said groove with a mask material, (ii) etching said gate electrode material until said gate insulative film, except for portions thereof beneath said mask material and over said groove, is exposed to thereby obtain a self-aligned gate electrode within said groove and a separate non-self-aligned gate electrode beneath said mask, a substantial portion of the self-aligned gate electrode being buried within the substrate such that the upper surface of the gate electrode is substantially even with or lower than the surface of the substrate surrounding the gate electrode; and

(e) forming source regions and drain regions in the substrate within the surface area defined by respective side portions of said oxide field regions by diffusing an impurity utilizing said groove filled with said gate electrode material, said field oxide regions, and said separate non-self-aligned gate electrode as masks.

4. The method of claim 3 wherein said step of simultaneously forming includes covering a second portion of said gate electrode material, inclusive of a part thereof over part of said groove, with said mask material whereby said etching obtains a lead integral with said self-aligned gate electrode.

5. In a method of manufacturing a self-aligned gate electrode and self-aligned source and drain regions located in a portion of semiconductor substrate between field oxide regions in a MOS semiconductor device, the improvement comprising the steps of:

(a) forming a groove substantially U-shaped in cross-section in a predetermined exposed portion of said semiconductor substrate where said self-aligned gate electrode is to be located;

(b) forming a gate insulation film to cover the surface of said substrate inclusive of said groove;

(c) depositing a gate electrode material on said substrate to a thickness t expressed by the formula;

space="preserve" listing-type="equation">t≧

(a/2) tan (45°

+θ

/2)

wherein;

a=the width of the groove opening; and

θ

=the angle at which the sides of the groove incline to the vertical to thereby fill said groove with said gate electrode material;

(d) forming a self-aligned gate electrode by etching away said gate electrode material until said gate insulation film, except for a portion thereof within said groove, is exposed thereby forming the gate electrode in a self-aligned manner, the gate electrode being substantially buried within the substrate such that the upper surface of the gate electrode is substantially even with or lower than the surface of the substrate surrounding the gate electrode; and

(e) forming source and drain regions between respective side portions of the field oxide regions and respective side portions of said groove filled with said gate material by diffusing an impurity utilizing said groove filled with said gate electrode material and said field oxide regions as masks to thereby form self-aligned source and drain regions substantially only within the substrate.

6. The method of claim 5 wherein said step of forming a self-aligned gate electrode includes covering a portion of said gate electrode material inclusive of a part thereof over part of said groove followed by said etching away of said gate electrode material until said gate insulation film, except for portions thereof beneath said mask material and over said groove, is exposed to thereby obtain a self-aligned gate electrode within said groove and a lead integral to said gate electrode.

7. In a method of manufacturing both a self-aligned gate electrode and a non-self-aligned gate electrode and respective source and drain regions located in a portion of semiconductor substrate between field oxide regions in a MOS semiconductor device, the improvement comprising the steps of:

(a) forming a groove substantially U-shaped in cross-section in a predetermined exposed portion of said semiconductor substrate where said self-aligned gate electrode is to be located;

(b) forming a gate insulation film to cover the surface of said substrate inclusive of said groove;

(c) depositing a gate electrode material on said substrate to a thickness t expressed by the formula;

space="preserve" listing-type="equation">t≧

(a/2) tan (45°

-θ

/2)

Wherein;

a=the width of the groove opening; and

θ

=the angle at which the sides of the groove include to the vertical to thereby fill said groove with said gate electrode material, said thickness t being sufficient enough to preclude formation of a hole in said groove;

(d) simultaneously forming both a self-aligned gate electrode and a non-self-aligned gate electrode by (i) covering a first portion of said gate electrode material remote from said groove with a mask material, (ii) etching said gate electrode material until said gate insulative film, except for portions thereof beneath said mask material and over said groove, is exposed to thereby obtain a self-aligned gate electrode within said groove and a separate non-self-aligned gate electrode beneath said mask a substantial portion of the self-aligned gate electrode being buried within the substrate such that the upper surface of the gate electrode is substantially even with or lower than the surface of the substrate surrounding the gate electrode; and

(e) forming source regions and drain regions in the substrate, within the surface area defined by respective side portions of said oxide field regions by diffusing an impurity utilizing said groove filled with said gate electrode material, said field oxide regions, and said separate non-self-aligned gate electrode as masks.

8. The method of claim 7 wherein said step of simultaneously forming includes covering a second portion of said gate electrode material, inclusive of a part thereof over part of said groove, with said mask material, whereby said etching obtains a lead integral with said self-aligned gate electrode.