Data processing system having multiple buses

• US 4,456,965 A
• Filed: 10/14/1980
• Issued: 06/26/1984
• Est. Priority Date: 10/14/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Someshwar, Ashok H., Graber, Warren S.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/196,892
• Time in Patent Office: 1,351 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/100
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.

Claims

1. A data processing system comprising:

a bus system including first, second, third and fourth N bit buses;

a plurality of logic blocks, at least a said logic block coupled to each one of said first, second, third and fourth buses for data transfer of N bit words;

a bus splitting circuit having a first state for coupling said first and second buses together and coupling said third and fourth buses together and having a second state for coupling said first and third buses together and coupling said second and fourth buses together.

2. A data processing system as claimed in claim 1, further comprising:

a control means for generating sets of control signals for control of said logic blocks and said bus splitting circuit, said control means including means for generating at least a first control signal of a said set of said control signals for placing said bus splitting circuit in said first state and causing data transfer between a logic block coupled to said first bus and a logic block coupled to said second bus or generating at least a second control signal of a said set of said control signals for placing said bus splitting circuit in said second state causing data transfer between a logic block coupled to said first bus and a logic block coupled to said third bus causing data transfer between a logic block coupled to said second bus and a logic block coupled to said fourth bus.

3. A data processing system as claimed in claim 2, wherein:

said logic blocks include a memory means for selectively storing an N bit data word received from said bus system at a memory location corresponding to an address signal received from said bus system and outputting an N bit data word to said bus system from a memory location corresponding to an address signal received from said bus system; and

said logic blocks further includes a memory pointer system having a plurality of address pointers for outputting an address signal from a selected one of said address pointers in response to a control signal from said control means.

4. A data processing system as claimed in claim 3, wherein:

said memory means system includes a random access memory coupled to both said second and fourth buses;

said memory pointer system includes a first address pointer coupled for outputting an address signal to said second bus and a second address pointer coupled for outputting an address signal to said fourth bus, said memory pointer system further including means for causing both said first and second address pointers to output address signals in response to a control signal; and

said control means further including means for generating at least one set of control signals for causing data transfer between a logic block coupled to said second bus and said memory location of said random access memory corresponding to said address signal outputted by said first address pointer and causing data transfer between a logic block coupled to said fourth bus and said memory location of said random access memory corresponding to said address signal outputted by said second address pointer.

5. A data processing system as claimed in claim 4, wherein:

said memory means further includes read only memory coupled for outputting an N bit data word to said first bus and to said fourth bus; and

said control means further including means for generating at least one set of control signals for placing said bus splitting circuit in said first state both to transfer data output from said read only memory corresponding to a first address signal outputted by said memory pointer system to a logic block coupled to said first or second bus and to transfer data from a memory location of said read only memory means corresponding to a second address signal outputted by said memory pointer system to a logic block coupled to said third and fourth bus, or said control means including means for generating at least one set of control signals for placing said bus splitting circuit in said second state both to transfer data from a memory location of said read only memory corresponding to a first address signal outputted by said memory pointer system to a logic block coupled to said first or third bus and to transfer data from a memory location of said read only memory means corresponding to a second address outputted by said memory pointer system to a logic block coupled to said second or fourth bus.