Channel address control system for a virtual machine system

• US 4,459,661 A
• Filed: 04/21/1982
• Issued: 07/10/1984
• Est. Priority Date: 09/18/1978
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ishibashi, Masamichi, Ikegami, Fujio, Kaneda, Saburo, Seta, Yoshikatsu
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/370,193
• Time in Patent Office: 811 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 718/100
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems

Abstract

A virtual machine system having a virtual storage function, wherein registers are provided for holding the heading and trailing addresses of the continuous area in the main storage area assigned respectively for each of the plural operating systems. When the main storage area is accessed by a channel or sub-channel, one of the registers is selected, and the heading address of the register selected is added to the main storage address sent from the channel or sub-channel. The added main storage address is compared with the trailing address in the selected register and if the former is smaller than the latter, the overhead for supporting the virtual storage area is reduced by accessing the main storage area in accordance with the added main storage address mentioned above.

Claims

1. A channel address control system for reducing the overhead for supporting the virtual storage function of a virtual machine system having a main storage area for storing data transfer instructions, channels for executing respective plural control programs, and a central processing unit for providing region identification information and for executing a monitor program for monitoring said plural control programs, said plural control programs being operated on the virtual machine system under the control of said monitor program, each of said channels providing a main storage address, continuous regions of the main storage area being exclusively assigned for access by corresponding ones of the plural control programs, respectively, each assigned continuous region being described by a heading address and a trailing address, comprising:

at least one register for storing, as identifying information, the heading addresses and trailing addresses of the continuous regions of the main storage area assigned to respective ones of the control programs;

transmission means, operatively connected to the central processing unit and to the channels, for transmitting the region identification information to identify one of the continuous regions to one of the channels;

first means, operatively connected to said transmission means and located in said one of the channels, for storing said region identification information;

second means, operatively connected to said at least one register, the channels, and to said main storage area, for adding the heading address of the continuous region identified by the region identification information stored in said first means to the main storage address provided by said one of the channels, so that a system absolute address is obtained; and

third means, operatively connected to said second means, said at least one register and to said central processing unit, for comparing said system absolute address with the trailing address of the continuous region identified by the region identification information, said third means transmitting an address exception signal to said central processing unit if the result of the comparison indicates that said system absolute address corresponds to a portion of the main storage area outside the continuous region identified by the region identification information, said main storage area being accessed in dependence upon said system absolute address, said transmission means comprising;

fourth means, operatively connected to the main storage area, for decoding one of the data transfer instructions for one of the channels;

fifth means, operatively connected to said fourth means, for storing the region identification information for said one of the channels; and

sixth means, operatively connected to said fifth means, for transmitting the region identification information to said one of the channels when the data transfer instruction is decoded, whereby the overhead for memory mapping is reduced.

2. A channel address control system for a virtual machine system as set forth in claim 1, wherein said transmission means further comprises:

seventh means, operatively connected to the central processing unit, for transmitting a channel command signal, including the region identification information, to one of the channels.

3. A channel address control system for a virtual machine system as set forth in claim 1 or 2, further comprising accessing means, operatively connected to said second means and the main storage area, for accessing the main storage area, wherein said accessing means includes a buffer mechanism.

4. A channel address control system for reducing the overhead for supporting the virtual storage function of a virtual machine system having a main storage area, a central processing unit for providing a currently effective storage number and for executing a monitor program for monitoring plural control programs, and an input/output unit, said main storage area storing address translation table data and instruction signal data, said plural control programs being operated on the virtual machine system under the control of the monitor program, said channel address control system comprising:

a storage control unit, operatively connected to said main storage area, for controlling the accessing of the main storage area;

a plurality of channels, operatively connected to said input/output unit, for respectively executing said plural control programs, each of said channels providing channel data including a first region identifier and channel address data;

and

a channel control unit, operatively connected to said storage control unit and to said plurality of channels, for controlling the flow of data to and from said plurality of channels;

said storage control unit comprising;

a first register, operatively connected to said main storage area, for storing said address translation table data read out from said main storage area;

a second register, operatively connected to said plurality of channels, for storing said channel address data;

a first region register, operatively connected to said plurality of channels, for storing said first region identifier sent from one of said plurality of channels;

a third register, operatively connected to said first region register, for storing address modification information, representing continuous regions of the main storage area exclusively assigned to respective ones of said plural control programs, a portion of said address modification information being selected in dependence upon the first region identifier;

a fourth register, operatively connected to said central processing unit, for storing the currently effective storage number representing one of said plural control programs;

a fifth register, operatively connected to said central processing unit, for storing logical address data and address in page data;

a high speed buffer circuit, operatively connected to said first register, for performing address translation and for providing an identification output representing one of the control programs, a physical address output, and a logical address output, said high speed buffer circuit being indexed by said logical address data;

a sixth register, operatively connected to said high speed buffer circuit, for reading and writing data to or from said high speed buffer circuit;

a first comparator circuit, operatively connected to said fifth register and said high speed buffer circuit, for comparing said logical address data with said logical address output and for providing a first coincidence output;

a second comparator circuit, operatively connected to said fourth register and said high speed buffer circuit, for comparing said currently effective storage number with said identification output and for providing a second coincidence output;

a seventh register for storing a segment table heading address;

a dynamic address translation adder circuit, having inputs and outputs, said inputs operatively connected to each of said seventh register, said fifth register, said third register, said second register and said first register, for adding address data and for providing a sum output;

an eight register, operatively connected to the outputs of said dynamic address translation adder circuit, for storing said sum output;

a third comparator circuit, operatively connected to said third register and said eighth register, for comparing said stored sum output to said selected address modification information and for providing an address exception signal to the central processing unit if the comparison result indicates that the stored sum output indicates an address in the main storage area outside the continuous region identified by the first region identifier;

a first selection gate, operatively connected to said first and second comparator circuits, said high speed buffer circuit, and said fifth register, for accessing the main storage area on the basis of the physical address output of said high speed buffer circuit and the address in page data stored by said fifth register in dependence upon the state of said first and second coincidence outputs; and

prefixing means, operatively connected to an input of said dynamic address translation adder circuit and to said eighth register, for performing prefix processing on the content of said eighth register and for providing a prefix processing output to the input of said dynamic address translation adder circuit, whereby the overhead for memory mapping is reduced.

5. A channel address control system for a virtual machine system as set forth in claim 4, further comprising an instruction unit operatively connected to said storage control unit, wherein said instruction unit comprises:

an instruction counter circuit, operatively connected to said fifth register, for counting instructions;

an instruction buffer circuit, operatively connected to said instruction counter circuit and to said storage control unit, for reading out said instruction signal data from the main storage area in dependence upon the count information of said instruction counter circuit;

an instruction decoder circuit, operatively connected to said instruction buffer circuit, for decoding said instruction signal data read out from the main storage area; and

a second region register, operatively connected to said instruction decoder circuit and to said channel control unit, for providing one of a plurality of region identifiers, as said first region identifier, to said channel control unit in dependence upon the output of said instruction decoder circuit.

6. A channel address control system for a virtual machine system as set forth in claim 5, wherein said instruction unit generates command and address signals, and flag information, and wherein said channel control unit comprises:

a data register, operatively connected to said storage control unit, for storing data to be sent to or received from the main storage area;

a ninth register, operatively connected to said instruction unit, for storing said command and address signals sent from said instruction unit;

a tenth register, operatively connected to said instruction unit, for storing said flag information and said count information received from said instruction unit;

a third region register, operatively connected to said plurality of channels and to said first region register, for storing said first region identifier;

an eleventh register, operatively connected to said plurality of channels and to said second register, for storing said channel address data; and

a channel selection control requester circuit, operatively connected to said storage control unit and to said plurality of channels, for controlling channel selection and requests to said storage control unit.

7. A channel address control system for a virtual machine system as set forth in claim 6, wherein said plurality of channels comprise a block multiplexer channel, operatively connected to said channel control unit and said input/output units, for multiplexing multiple byte data;

and

a byte multiplexer channel, operatively connected to said channel control unit and said input/output units, for multiplexing single byte data.

8. A channel address control system for a virtual machine system as set forth in claim 7, wherein said block multiplexer channel comprises:

a fourth region register, operatively connected to said second region register and said third region register, for storing said first region identifier;

a twelfth register, operatively connected to said ninth register and said eleventh register, for storing said address signal sent from said instruction unit;

a thirteenth register, operatively connected to said storage control unit and said input/output units, for storing multiple byte input data;

a fourteenth register, operatively connected to said storage control unit and said input/output units, for storing multiple byte output data.

9. A channel address control system for a virtual machine system as set forth in claim 8, wherein said byte multiplexer channel comprises:

a fifth region register, operatively connected to said second region register and said third region register, for storing said first region identifier;

a fifteenth register, operatively connected to said ninth register and said eleventh register, for storing said address signal sent from said instruction unit;

a sixteenth register, operatively connected to said thirteenth register and said input/output units, for storing single byte input data; and

a seventeenth register, operatively connected to said fourteenth register and said input/output units, for storing single byte output data.

10. A channel address control system for a virtual machine system as set forth in claim 5, wherein said instruction unit generates command and address signals, and flag information, and wherein said channel control unit comprises:

a data register, operatively connected to said storage control unit, for storing data to be sent to or received from the main storage area;

a ninth register, operatively connected to said instruction unit, for storing said command and address signals sent from said instruction unit;

a tenth register, operatively connected to said instruction unit, for storing said flag information, said count information, and said first region identifier received from said instruction unit;

a third region register, operatively connected to said plurality of channels and to said first region register, for storing said first region identifier;

an eleventh register, operatively connected to said plurality of channels and to said second register, for storing said channel address data; and

a channel selection control request circuit, operatively connected to said storage control unit and to said plurality of channels, for controlling channel selection and requests to said storage control unit.

11. A channel address control system for a virtual machine system as set forth in claim 10, wherein said plurality of channels comprise a block multiplexer, operatively connected to said channel control unit and said input/output units, for multiplexing multiple byte data;

and

a byte multiplexer channel, operatively connected to said channel control unit and said input/output units, for multiplexing single byte data.

12. A channel address control system for a virtual machine system as set forth in claim 11, wherein said block multiplexer channel comprises:

a fourth region register, operatively connected to said tenth register and said third region register, for storing said first region identifier;

a twelth register, operatively connected to said ninth register and said eleventh register, for storing said address signal sent from said instruction unit;

a thirteenth register, operatively connected to said storage control unit and said input/output units, for storing multiple byte input data;

a fourteenth register, operatively connected to said storage control unit and said input/output units, for storing multiple byte output data.

13. A channel address control system for a virtual machine system as set forth in claim 12, wherein said byte multiplexer channel comprises:

a fifth region register, operatively connected to said tenth register, for storing said first region identifier;

a fifteenth register, operatively connected to said ninth register, and said eleventh register, for storing said address signal sent from said instruction unit;

a sixteenth register, operatively connected to said thirteenth register and said input/output units, for containing single byte input data; and

a seventeenth register, operatively connected to said fourteenth register and said input/output units, for containing single byte output data.

14. A channel address control system for reducing the overhead for supporting the virtual storage function of a virtual machine system having a main storage area for storing data transfer instructions, and a central processing unit for providing a currently effective storage number and for executing a monitor program for monitoring plural control programs, said plural control programs being operated on the virtual machine system under the control of the monitor program, said channel address control system comprising:

a storage control unit, operatively connected to said main storage area, for controlling the accessing of the main storage area;

a plurality of channels, for respectively executing said plural control programs, each of said channels providing a first region identifier and channel address data;

a channel control unit, operatively connected to said storage control unit and to said plurality of channels, for controlling the flow of data to and from said plurality of channels; and

an instruction unit;

said storage control unit comprising;

a first register, operatively connected to said plurality of channels, for storing said channel address data;

a second register, operatively connected to said plurality of channels, for storing the first region identifier sent from one of said plurality of channels;

a third register, operatively connected to said second register, for storing address modification information representing continuous regions of the main storage area exclusively assigned to respective ones of said plural control programs, a portion of said address modification information being selected in dependence upon the first region identifier;

a dynamic address translation adder circuit, operatively connected to said first register and said third register, for adding said channel address data to the selected address modification information to generate a system absolute address for accessing said main storage area;

a comparator circuit, operatively connected to said dynamic address translation adder circuit and said third register, for comparing said sum output to said selected address modification information and for transmitting an address exception signal to the central processing unit if the comparison result indicates that the system absolute address is an address in the main storage area outside the continuous region identified by said first region identifier;

said instruction unit comprising;

first means, operatively connected to the main storage area, for decoding one of the data transfer instructions for one of said plurality of channels;

second means, operatively connected to said first means, for storing region identification information for said one of said plurality of channels, the region identification information indicating the one of the continuous regions of the main storage area exclusively assigned to the corresponding said one of said plural control programs;

said channel control unit comprising third means, operatively connected to said second means, for transmitting the region identification information to said one of said plurality of channels when the data transfer instruction is decoded, the region identification information corresponding to the first region identifier for said one of the plurality of channels, whereby the overhead for memory mapping is reduced.