Decoder

• US 4,459,672 A
• Filed: 07/19/1982
• Issued: 07/10/1984
• Est. Priority Date: 02/27/1980
• Status: Expired due to Term

• Current Assignee: Summit Business Capital Corp. (Bank of America Corp.)
• Original Assignee: Regency Electronics Incorporated (BK Technologies Corp.)
• Inventors: Koch, Richard C., Buennagel, James A.
• Primary Examiner(s): Gruber, Felix D.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/399,755
• Time in Patent Office: 722 Days
• Field of Search: 364/900 MS File, 364/200 MS File, 364/492, 364/493, 364/484, 364/487, 179/84 VF, 340/825.71
• US Class Current: 702/78
• CPC Class Codes: G08C 25/00 Arrangements for preventing or correcting errors; Monitoring arrangements
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A load management system which includes a central message generator and a plurality of addressable remote load controllers which selectively connect and disconnect high power deferrable loads to and from a power source in response to transmitted messages. The load controllers include means for translating coded tone pair inputs into digital data. Tones selected from three such tone pairs are used in one scheme, where a tone selected from the first tone pair is used for the initial bit of a message, and subsequent tones are alternately selected from the remaining two tone pairs or the remaining bits. One of the tones of the first tone pair is utilized as a test tone which initiates a test routine sequence. The test tone can be transmitted by a portable, low power transmitter to test the functioning of the remote units. A message format includes two code sets, a zone code set and a command/address code set. Each load controller has a preprogrammed zone identifier and a preprogrammed address identifier, and is responsive to a command/address code message only when the last received zone code message has identified the preprogrammed zone identifier of that load controller and the command/address message indicates the preprogrammed address identifier of that load controller. All load controllers having a common zone identifier are responsive to a scram instruction message which identifies that zone.

Claims

1. A decoder for decoding received input frequency data into digital data, the input frequency data corresponding to a plurality of bits, for each bit there being at least a pair of tones with the upper tone of said pair indicating a first logic state and the lower tone of said pair indicating a second logic state, with sequential bits being different tone pairs, said tones having associated oscillation cycles, said decoder comprising:

a. input means for detecting a particular phase in the cycle of a tone, said input means having an output and an input;

b. N window registers, each register having an input and an output, each register including means for accumulating single bit data applied to its input;

c. sequencing means for repetitively and sequentially applying the output of said input means to the inputs of a number N of said window registers, said sequencing means including means for sequenctially applying the output of said input means to the inputs of N window registers at a regular rate during a base period of time which is an integer X times the period of said upper tone and an integer Y times the period of said lower tone, said repetitive and sequential application forming a pattern of data in said N window registers;

d. means for detecting repetition in the pattern of data in said N window registers and for generating a first logic signal where there is repetition in each (N/X)^th window register, and for generating a second logic signal where there is repetition in each (N/Y)^th window register; and

e. alternating means for permitting alternate sensitivity for tone detection from different tone pairs corresponding to consecutive sequential bits, neither tone in the one tone pair being the same as a tone in the other, said alternating means preventing sensitivity to tones in said one tone pair when detecting said other tone pair and being insensitive to tones in said other tone pair when detecting said one tone pair.

2. The decoder of claim 1 in which said frequencies are between about 400 Hz and about 1,300 Hz.

3. The decoder of claim 2 in which for each bit the base period of said sequencing means is two times the period of said lower tone and three times the period of said upper tone.

4. The decoder of claim 1 in which there are three tone pairs, with the decoder being sensitive to only one of said tone pairs if it has not received other tones within a predetermined period of time.

5. A decoder for decoding received in put frequency data into digital data, the input frequency data being a sequence of audio frequency tones, said tones having associated oscillation cycles, said decoder comprising:

a. input means for detecting a particular phase in the cycle of a tone, said input means having an output and an input;

at least a number N of window registers, each register having an input and an output, each register including means for accumulating single bit data applied to its input;

c. sequencing means for repetitively and sequentially applying the output of said input means to the inputs of N said window registers, said sequencing means including means for sequenctially applying the output of said input means to the inputs of N window registers at a regular rate during a base period of time which is an integer X times the period of the tone to be sensed, said repetitive and sequential application forming a pattern of data in said N window registers;

d. detecting means for detecting repetition in the pattern of data in said N window registers and for generating a logic signal where there is repetition in each (N/X)^th window register;

e. means for counting the outputs of said input means and for activating said detecting means after a predetermined count;

f. said detecting means including means for generating said logic signal when the repetition in each (N/X)^th window register is less than 90% of the predetermined count and for not generating said logic signal when the repetition in each (N/X)^th window register is only 50% or lower;

g. stepping means for causing said decoder to be sensitive to a different tone when a sensed for tone is detected; and

h. means for resetting said decoder to be sensitive to a specific tone if a logic signal is not generated by said detecting means within a predetermined period of time.

6. The decoder of claim 5 in which said stepping means includes means for changing the base period during which N window registers are sequenced by said sequencing means.

7. The decoder of claim 5 in which said detecting means generates one of said logic signals only if the total repetition in the respective window registers is at least about 65% of the theoretical value.

8. The decoder of claim 5 in which said detecting means includes means for adding pairs of adjacent window registers in detecting repetition in the pattern of window registers.

9. The decoder of claim 5 in which said input means includes a zero crossover detector.

10. The decoder of claim 5 in which said frequencies are between about 400 Hz and about 1,300 Hz.

11. A decoder for decoding received input frequency data into digital data, the input frequency data corresponding to a plurality of bits, for each bit there being at least a pair of tones with the upper tone of said paid indicating a first logic state and the lower tone of said pair indicating a second logic state, with sequential bits being different tone pairs, said tones having associated oscillation cycles, said decoder comprising:

a. input means for detecting a particular phase in the cycle of a tone, said input means having an output and an input;

b. at least a number N of window registers, each register having an input and an output, each register including means for accumulating single bit data applied to its input;

c. sequencing means for repetitively and sequentially applying the output of said input means to the inputs of a number N of said window registers, said sequencing means including means for sequenctially applying the output of said input means to the inputs of N of said window registers at a regular rate during a base period of time which is an integer X times the period of said upper tone and an integer Y times the period of said lower tone, said repetitive and sequential application forming a pattern of data in said N window registers;

d. means for detecting repetition in the pattern of data in said N window registers and for generating a first logic signal where there is repetition in each (N/X)^th window register, and for generating a second local signal where there is repetition in each (N/Y)^th window register;

e. means for counting the outputs of said input means and for activating said detecting means after a predetermined count;

f. said detecting means including means for generating one of said logic signals when the detected repetition is less than 90% and greater than 50% of the predetermined count;

g. stepping means for causing said decoder to be sensitive to a different tone pair when a sensed for tone is detected; and

h. means for resetting said decoder to be sensitive to a specific tone pair if a logic signal is not generated by said detecting means within a predetermined period of time.

12. The decoder of claim 11 in which said stepping means includes means for changing the base period during which N window registers are sequenced by said sequencing means.

13. The decoder of claim 11 in which said detecting means generates one of said logic signals only if the total repetition in the respective window registers is at least about 65% of the theoretical value.

14. The decoder of claim 11 in which said detecting means includes means for adding pairs of adjacent window registers in detecting repetition in the pattern of window registers.

15. The decoder of claim 11 in which said input means includes a zero crossover detector.

16. The decoder of claim 11 in which said frequencies are between about 400 Hz and about 1,300 Hz.