Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

• US 4,460,835 A
• Filed: 05/06/1981
• Issued: 07/17/1984
• Est. Priority Date: 05/13/1980
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Masuoka, Fujio
• Primary Examiner(s): Anagnos, Larry N.
• Assistant Examiner(s): Hudspeth, David R.
• Application Number:
  US06/260,994
• Time in Patent Office: 1,168 Days
• Field of Search: 307/296 A, 307/296 R, 307/278, 307/291, 307/448, 307/450, 307/465, 307/572, 307/577, 307/581, 307/304, 357/23 D, 357/23 R, 357/89
• US Class Current: 327/536
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H03K 19/09443 using a combination of enhancement and depletion transistors
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03K 3/35606 with synchronous operation

Abstract

A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor logic circuit operable both in active and standby modes; and

on-chip substrate bias generating means, including an input terminal responsive to a mode control signal having first and second signal levels respectively corresponding to said active and standby modes, for providing a first on-chip substrate bias voltage to said semiconductor logic circuit in said active mode in response to said first signal level and a second on-chip substrate bias voltage of a different value in said standby mode in response to said second signal level, thereby reducing the power consumption of both said logic circuit and said substrate bias generating means during said standby mode.

4. A semiconductor integrated circuit device according to claim 1, wherein said on-chip substrate bias generating means includes a first generator for generating a first on-chip substrate bias voltage at the time of said active mode and a second generator for generating a second on-chip substrate bias voltage at the time of said standby mode.

5. A semiconductor integrated circuit device according to claim 1, wherein said semiconductor logic circuit is a MOS inverter including a mode switching transistor having a gate for receiving a chip enable signal and a drain-source current path connected between a power supply terminal and a node, a load element connected between said node and an output terminal, and a transistor having a gate receiving an input signal and a drain-source current path connected between said output terminal and ground.

9. A semiconductor integrated circuit device according to claim 1 or 2, wherein said first generator includes an oscillator, an amplifier for amplifying the output of said oscillator and a charge pump circuit having a construction consisting of at least one stage for imparting the output of said amplifier with a predetermined level.

2. A semiconductor integrated circuit device comprising:

a semiconductor logic circuit operable both in active and standby modes; and

on-chip substrate bias generating means for providing a first on-chip substrate bias voltage to said semiconductor logic circuit in said active mode and a second on-chip bias voltage of a different value in said standby mode, wherein said on-chip substrate bias generating means includes a first generator for generating said first on-chip substrate bias voltage at the time of said active mode and a second generator for generating said second on-chip substrate bias voltage at the time of said standby mode.

8. A semiconductor integrated circuit device according to claim 2 or 4, wherein the frequency of said second on-chip substrate bias voltage generated from said second generator is set to a value within a range of 1/10 to 1/100 of the frequency of the first on-chip substrate bias voltage generated from said first generator.

10. A semiconductor integrated circuit device according to claim 2 or 4, wherein said second generator includes an oscillator, an amplifier for amplifying the output of said oscillator circuit, and a charge pump circuit having a construction consisting of a plurality of stages for increasing the bias voltage level of the output signal from said amplifier.

3. A semiconductor integrated circuit device comprising:

a semiconductor logic circuit operable both in active and standby modes, wherein said semiconductor logic circuit is a MOS inverter including a mode switching transistor having a gate for receiving a chip enable signal and a drain-source current path connected between a power supply terminal and a node, a load element connected between said node and an output terminal, and a transistor having a gate receiving an input signal and a drain-source current path connected between said output terminal and ground; and

on-chip substrate bias generating means for providing a first on-chip substrate bias voltage to said semiconductor logic circuit in said active mode and a second on-chip substrate bias voltage of a different value in said standby mode.

6. A semiconductor integrated circuit device according to claim 3 or 5, wherein said load element is a load MOS transistor.

7. A semiconductor integrated circuit device according to claim 3 or 5, wherein said load element is a resistor.

11. A semiconductor integrated circuit device according to claim 3 or 5, wherein said mode switching transistor functions as a weak depletion or depletion type MOS transistor for causing sufficient current with a first back gate bias given in said active mode and functions as an enhancement-type MOS transistor for substantially cutting off current with a second back gate bias given in said standby mode.

12. A semiconductor integrated circuit device according to claim 3 or 5, wherein the threshold voltage of said mode switching transistor is substantially zero volt determined by the substrate bias voltage in the active mode and sharply increases with a voltage less than the substrate bias that is given in the standby mode.

13. A semiconductor integrated circuit device according to claim 12, wherein the impurity concentration of the portion of the semiconductor substrate on which said mode switching transistor is made sharply increases at a depth intermediate between the bottom of a depletion layer formed with the first on-chip substrate bias given in the active mode and the bottom of a depletion layer formed with the second on-chip substrate bias given in the standby mode.

14. A semiconductor integrated circuit device comprising an integrated circuit including first and second MOS inverters each including a load resistor provided between a first voltage supply terminal and an output terminal and a drive element having its drain-source current path connected between a second voltage supply terminal and said output terminal, the output terminal of said first MOS inverter being connected to the gate electrode of the drive element in said second MOS inverter, the output terminal of said second MOS inverter being connected to the gate electrode of the drive element in said first MOS inverter, a transfer element being connected to the output terminal of each of said first and second MOS inverters for transferring an output signal therefrom, and bias voltage generating means for generating a first on-chip substrate bias voltage with respect to the semiconductor substrate of said integrated circuit in a first mode and a second on-chip substrate bias voltage in a second mode, whereby the current level in each of said load resistors is substantially unaffected by the on-chip substrate bias changing between said first voltage and said second voltage.