Digital signal receiver

• US 4,461,002 A
• Filed: 01/19/1982
• Issued: 07/17/1984
• Est. Priority Date: 04/07/1981
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Nanko, Hideaki
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/340,829
• Time in Patent Office: 910 Days
• Field of Search: 371/47, 371/42, 371/61, 375/111, 375/118
• US Class Current: 714/798
• CPC Class Codes: H04N 7/0357 for error detection or correction

Abstract

A digital signal receiver is structured to receive and demodulate a digital signal. Such digital signal may comprise, for example, a television signal of character multiplex transmission having a digital signal included in the vertical blanking period of the television signal and a digital signal receiver may be structured to reproduce the digital signal from the television signal. The digital signal includes a clock run-in signal (CRI), a framing code signal (FRC) and a bit serial data signal (DA) disposed in succession. An error of the framing code or the data signal caused by a low frequency region group delay characteristic of a transmission path between the transmission and the demodulation is detected based on the digital signal. Upon detection of an error, a waveform distortion of the framing code signal and the data signal is corrected by means of a correcting circuit (15) such as an LC circuit, whereby an error of the data signal to be demodulated thereafter is prevented.

Claims

1. A digital signal receiver for receiving a digital signal being transmitted, said digital signal including a data signal of a bit serial fashion including data, and a specified code signal preceding said data signal, comprising:

demodulating means for receiving and demodulating said digital signal,

sampling clock generating means for generating a sampling clock signal for use in sampling said demodulated digital signal,

sampling means responsive to the output of said sampling clock generating means for reproducing said data signal by sampling said demodulated digital signal,

error detecting means responsive to said demodulated digital signal for detecting an error in bit phase of said demodulated digital signal caused by a group delay characteristic of a transmission path between transmission and demodulation with respect to detection of said specified code signal as demodulated, and

digital signal phase shifting means coupled between said demodulating means and said sampling means for shifting the phase of said demodulated digital signal, said shifting means responsive to the error detection output of said error detecting means for correcting said bit phase error.

2. A digital signal receiver in accordance with claim 1,

wherein said digital signal phase shifting means comprises digital signal phase lagging circuit for lagging the phase of said digital signal as demodulated.

3. A digital signal receiver in accordance with claim 1, wherein

said digital signal phase shifting means comprises digital signal phase advancing circuit for advancing the phase of said digital signal as demodulated.

4. A digital signal receiver in accordance with claim 1, wherein

said group delay characteristic is of a phase advanced characteristic or a phase lagged characteristic, and

said digital signal phase shifting means comprises

digital signal phase lagging circuit for lagging the phase of said digital signal as demodulated, and

digital signal phase advancing circuit for advancing the filter of said digital signal as demodulated, and which further comprises

phase determining means for determining whether said group delay characteristic is of an advanced phase or a lagged phase, and

digital signal phase advancing/lagging circuit selecting means responsive to the phase advanced determining output of said phase determining means for selecting said digital signal phase lagging circuit and responsive to the lagged phase determining output of said phase determining means for selecting said digital signal phase advancing circuit.

5. A digital signal receiver in accordance with claim 1, wherein

said error detecting means comprises non-coincidence detecting means for detecting non-coincidence of a predetermined code signal and said specified code signal as demodulated.

10. A digital signal receiver in accordance with claim 4 or 9, wherein

said specified code signal comprises a plurality of bits and is selected to maintain a first level continually for a period of a plurality of bits, and

said phase determining means comprises bit non-coincidence detecting means for detecting non-coincidence of a first bit and a final bit out of said plurality of predetermined bits where said first level is continuously maintained with said predetermined code signal for determining whether said group delay characteristic is of an advanced phase or a lagged phase.

11. A digital signal receiver in accordance with claim 1 or 6, wherein

said error detecting means comprises parity check means for performing a parity check of said said signal as demodulated for detecting whether said data signal involves an error or not.

6. A digital signal receiver for receiving a digital signal being transmitted, said digital signal including a data signal of a bit serial fashion including data, and specified code signal preceding said data signal, comprising:

demodulating means for receiving and demodulating said digital signal,

sampling clock generating means for generating a sampling clock signal for use in sampling said demodulated digital signal,

sampling means responsive to said sampling clock signal obtained from said sampling clock generating means for reproducing said data signal by sampling said demodulated digital signal,

error detecting means responsive to said demodulated digital signal for detecting an error in bit phase of said demodulated digital signal caused by a group delay characteristic of a transmission path between transmission and demodulation with respect to detecting of said demodulated specified code signal, wherein said error detecting means comprises non-coincidence detecting means for detecting non-coincidence of a predetermined code signal and said demodulated specified code signal, and

sampling clock phase shifting means responsive to error detection by said error detecting means for shifting the phase of said sampling clock signal so as to coincide with the phase of said demodulated data signal.

7. A digital signal receiver in accordance with claim 6, wherein

said sampling clock phase shifting circuit comprises sampling clock phase advancing means for advancing the phase of said sampling clock.

8. A digital signal receiver in accordance with claim 6, wherein

said sampling clock phase shifting means comprises sampling clock phase lagging circuit for lagging the phase of said sampling clock.

9. A digital signal receiver in accordance with claim 6, wherein

said group delay characteristic is of a phase advanced characteristic or a phase lagged characteristic, and

said sampling clock phase shifting means comprises

sampling clock phase advancing circuit for advancing the phase of said sampling clock, and

sampling clock phase lagging circuit for lagging the phase of said sampling clock, and which further comprises

phase determining means for determining whether said group delay characteristic is of an advanced phase or a lagged phase, and

sampling clock phase advancing/lagging circuit selecting means responsive to the phase advanced determining output of said phase determining means for selecting said sampling clock phase advancing circuit and responsive to the phase lagged determining output of said phase determining means for selecting said sampling clock phase lagging circuit.