Frequency modulation transmitter for voice or data

• US 4,461,013 A
• Filed: 12/06/1982
• Issued: 07/17/1984
• Est. Priority Date: 04/06/1981
• Status: Expired due to Fees

• Current Assignee: AT&T, Inc.
• Original Assignee: AT&T, Inc.
• Inventors: Lese, Gregory, Nash, Donald H.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Watkins, Albert W.
• Application Number:
  US06/447,019
• Time in Patent Office: 589 Days
• Field of Search: 375/62, 375/65, 455/608, 455/614, 455/615, 455/618, 340/636, 320/48, 331/179, 331/51, 332/16 R, 332/20, 332/29 R, 332/10, 332/9 R, 377/44, 377/52
• US Class Current: 375/306
• CPC Class Codes: H03J 9/06 using electromagnetic waves other than radio waves, e.g. light
• CPC Class Codes: H04B 10/50 Transmitters
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision
• CPC Class Codes: H04M 11/085 using a television receiver, e.g. viewdata system

Abstract

A portable frequency modulation transmitter (1) for voice or data is disclosed for operation at infrared frequencies. The transmitter comprises keyboard (200) or microphone (402) input capability and dual modes of use. In the data mode, carrier is generated when the keyboard is operated and is not generated when the keyboard is idle in order to conserve power. In the voice mode, either voice or data may be transmitted, data having priority over voice. A series connection of two variable modulus counters (302, 303) and other counters (304, 305, 306) provide a frequency shift keyed data signal, marker data signal, marker data frames between data frames, parity insertion and other features. In the event that the local battery power level falls below a particular level, a particular word is inserted in the applied binary data input.

Claims

1. A frequency shift keyed signal generator circuit

characterized by

a first variable modulus counter (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B),

a second variable modulus counter (303), responsive to the applied input signal (A) and the frequency shift keyed output signal (B) of the first variable modulus counter (302), for dividing the frequency shift keyed output signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and

a data bit counter (304), responsive to the output of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.

3. A frequency shift keyed signal generator circuit as recited in claim 1 or 2

further characterized by

a data selector circuit (301), for inserting a flip bit in the applied binary data input (A), the flip bit for assisting a receive terminal to distinguish between a break in data transmission and a multiple transmission of the same data.

4. A frequency shift keyed signal generator circuit as recited in claim 3

further characterized in that

the data selector circuit (301) additionally inserts a parity bit, dependent on the flip bit, in the applied binary data input (A).

5. A frequency shift keyed signal generator circuit as recited in claim 1

further characterized by

a low battery indicating circuit (203, 212, 213, 301), responsive to a control signal indicating a low battery condition, for inserting a particular code for the low battery condition in the applied binary data input.

6. A frequency shift keyed signal generator circuit as recited in claim 5

further characterized in that

the low battery indicating circuit comprises a low battery code inhibit circuit (203), responsive to a data signal, for inhibiting the insertion of the particular low battery code in the presence of the data signal.

7. A frequency shift keyed signal generator circuit as recited in claim 1

further characterized by

a data selector circuit (301) for inserting a flip bit having a particular periodic location in the applied binary data input (A).

8. A frequency shift keyed signal generator circuit as recited in claim 1

further characterized by

a marker data counter (305), responsive to the data bit counter (304), for providing a control signal (G) to the first variable modulus counter (302), the control signal regulating the provision of marker data.

9. A frequency shift keyed signal generator circuit as recited in claim 8

further characterized by

a frame counter (306), responsive to the marker/data counter.

2. A frequency shift keyed signal generator circuit

characterized by

means (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B),

means (303), responsive to the applied input signal (A) and the frequency shift keyed signal (B), for dividing the frequency shift keyed signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and

means (304), responsive to the output (C) of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.