Process for etching tapered vias in silicon dioxide

• US 4,461,672 A
• Filed: 11/18/1982
• Issued: 07/24/1984
• Est. Priority Date: 11/18/1982
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Musser, Mary E.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/442,826
• Time in Patent Office: 614 Days
• Field of Search: 156/643, 156/646, 156/644, 156/652, 156/653, 156/657, 156/659.1, 156/662, 156/651, 204/192 E, 204/164, 427/38, 427/39, 427/88, 427/89, 427/90, 252/79.1
• US Class Current: 438/479
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/76804 by forming tapered via holes

Abstract

A method for etching tapered apertures in the insulating layer between metal layers in an integrated circuit having a multilevel interconnection system. In one embodiment a thin layer of polysilicon is formed on the interlevel oxide layer followed by deposition of a photoresist layer thereon. A pattern of apertures is formed in the resist layer which is then exposed to a selective silicon etchant to form an opening in the polysilicon layer extending to the surface of the oxide layer. The polysilicon and oxide layers are then etched with a nonselective etchant. During the oxide etch the polysilicon is etched laterally, thereby widening the apertures and producing a taper in the aperture sidewalls as the etch proceeds. The magnitude of the taper is related to the thickness of the polysilicon layer. In another embodiment wherein the oxide layer directly overlies a silicon region, the polysilicon and oxide layers are first exposed to a nonselective etchant to etch partially through the oxide layer. The tapered via is completed by etching through the oxide layer with a selective etchant.

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

forming an insulating layer on a surface of a semiconductor body;

depositing a semiconductor layer of a predetermined thickness on said insulating layer;

selectively masking said semiconductor layer with an apertured resist;

exposing said device to a selective etchant to form an opening in said semiconductor layer extending to the surface of said insulating layer; and

exposing said device to a nonselective etchant for etching said semiconductor layer and said insulating layer at predetermined rates, whereby tapered apertures are formed in said insulating layer.

2. The method of claim 1, wherein the magnitude of said taper is determined by selecting the appropriate thickness of said semiconductor layer.

3. The method of claim 2 wherein said insulating layer comprises silicon dioxide and said semiconductor layer comprises polysilicon.

4. A method for fabricating a semiconductor device comprising the steps of:

depositing a layer of silicon dioxide on a silicon substrate, said substrate including a patterned conducting layer thereon;

depositing a layer of polysilicon of a predetermined thickness on said silicon dioxide layer;

selectively masking said polysilicon layer with an apertured resist;

exposing said device to a selective etchant to form an opening in said polysilicon layer extending to the surface of said silicon dioxide layer; and

exposing said device to a nonselective etchant for etching said polysilicon layer and said silicon dioxide layer at predetermined rates, whereby tapered apertures are formed in said silicon dioxide layer extending to said conducting layer.

5. The method of claim 4 wherein said predetermined etch rates are selected so that the etch rate of polysilicon is substantially equal to the etch rate of silicon dioxide.

6. The method of claim 5 wherein the magnitude of said taper is determined by selecting the appropriate thickness of said polysilicon layer.

7. The method of claim 6, further including the steps of:

removing said apertured resist;

forming a second patterned metal layer overlying said polysilicon layer and said aperture, whereby an electrical connection is established between said second metal layer and said first metal layer through said aperture.

8. A method for fabricating a semiconductor device comprising the steps of:

forming an insulating layer on a surface of a semiconductor body;

depositing a semiconductor layer of a predetermined thickness on said insulating layer;

selectively masking said semiconductor layer with an apertured resist;

exposing said insulating layer to a first etchant nonselective as between said semiconductor and said insulator for a length of time sufficient to etch partially through said insulating layer, whereby a thin insulating region remains over said substrate; and

exposing said insulating layer to a second etchant selective for said insulator to etch through said thin insulating region to form an aperture in said insulating layer having tapered sidewalls.

9. The method of claim 8 wherein the magnitude of the taper of said aperture sidewalls is determined by selecting the appropriate thickness of said semiconductor layer.

10. The method of claim 9 wherein said insulating layer comprises silicon dioxide and said semiconductor layer comprises polysilicon.