Access control logic for video terminal display memory

• US 4,462,028 A
• Filed: 02/19/1981
• Issued: 07/24/1984
• Est. Priority Date: 02/19/1981
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Watkins, Richard R., Ryan, Joseph L., Kobs, Frederick E., Safdie, Elias
• Primary Examiner(s): TRAFTON, DAVID
• Application Number:
  US06/235,819
• Time in Patent Office: 1,251 Days
• Field of Search: 340/721, 340/723, 340/728, 340/731, 340/747, 340/748, 340/703, 340/799
• US Class Current: 345/567
• CPC Class Codes: G09G 5/222 Control of the character-code memory

Abstract

A logical control system is provided for accommodating both single and double byte accesses to a video terminal system display memory to supply video character and visual attribute data to a video screen without limiting the quantity of visual attributes and without the needless occupation of video screen character positions by visual attribute characters.

Claims

1. A video control system for accomodating display memory accesses in a video terminal system having video display logic, and further having a CPU and a timing control system electrically connected to a system data bus, said video control system comprising:

CRT control means for supplying binary address codes representative of video characters and visual attributes;

logic multiplexer address means responsive to a first character clock control signal from said timing control system for selecting between binary address codes for a single byte access received from said CPU representative of video characters or visual attributes and binary address codes for a double byte access received from said CRT control means representative of video characters and visual attributes;

logic random access memory means including video character memory byte segments and visual attribute memory byte segments responsive to a read/write mode selection control signal issued by said CPU, for receiving binary video character and visual attribute address codes from said logic multiplexer address means and supplying both a video character data byte and a visual attribute data byte either singly in response to an address from the CPU or concurrently in response to an address from the CRT control means;

logic memory segment selection means responsive to a first logic memory segment control signal received from said logic multiplexer address means, to a second logic memory segment control signal received from said CPU, and to a second character clock control signal received from said timing control system for enabling either a memory segment pair including a video character memory segment and a visual attribute memory segment, or one member of said memory segment pair; and

data buffer means responsive to enable control signals received from said CPU and to said first and said second character clock control signals for applying both a visual attribute data byte and a video character data byte from said memory segment pair to said video display logic, and applying a data byte from said one member of said memory segment pair to said data bus.

2. A video control system for a video terminal having video display logic, and further having a central processing unit (CPU) and a timing control system each electrically connected to the other by common system address, data and control busses, said video control system comprising:

CRT control means for supplying address codes and a first memory control signal;

logic multiplexer means in electrical communication with said CRT control means and said address bus, and responsive to a first time divided character clock control signal generated by said timing control system to receive binary address codes from said CRT control means or from said CPU for supplying binary video character and visual attribute address codes;

logic memory means including plural memory segment pairs wherein one member of each of said segment pairs is a video character byte memory and a second member of each of said segment pairs is a visual attribute byte memory, and wherein both members of a segment pair have like memory location addresses;

logic memory selection means responsive to said first memory control signal, to a second memory control signal received from said CPU by way of said address bus, and to a second time divided character clock control signal received from said timing control system for selectively enabling both members of any one of said segment pairs or any single member of a selected one of said segment pairs;

data buffer register means responsive to an enable control signal issued by said CPU and to said first character clock control signal for transferring data issued by a single enabled member of a segment pair to said data bus;

video data register means responsive to said second character control signal for receiving both video character and visual attribute data issued by an enabled segment pair for transfer to said video display logic;

first tristate bidirectional communication bus means electrically interconnecting input/output ports of each video character memory segment with video character input/output ports of said data buffer register means and said video data register mean; and

second tristate bidirectional communication bus means electrically interconnecting input/output ports of each visual attribute memory segment with visual attribute input/output ports of said buffer register means and said video data register means.

3. A video control system for a video terminal system having video display logic, a CPU and a timing control system, said video control system comprising:

random access memory for storing video character data bytes and visual attribute data bytes in respective memory segments, the least significant bits of binary addresses to the memory corresponding to both video character data bytes and associated visual attribute data bytes;

CRT control means for supplying binary address codes for simultaneously accessing both video character data bytes and associated visual attribute data bytes from the random access memory;

an address multiplexer logic unit for selecting between the address codes from said CRT control means and address codes from an address bus from said CPU, the address codes from the CPU comprising a segment selecting address bit to select between video character data bytes and visual attribute data bytes to provide for a single byte access of either a video character data byte or a visual attribute data byte, the logic unit comprising means for enabling both video character and visual attribute memory segments when address codes from the CRT control means are selected and for enabling only the memory segment indicated by the segment selecting bit when address codes from the CPU are selected;

a first, bidirectional data buffer between the random access memory and data bus to said CPU;

a second data buffer between the random access memory and said video display logic; and

means responsive to control signals from the CPU and the timing control system for writing single bytes of data from the CPU data bus through the first data buffer into memory locations addressed by the CPU, for reading single bytes of data, from memory locations addressed by the CPU, through the first data buffer to the CPU data bus, and for reading parallel video character and visual attribute data bytes, from memory locations addressed by said CRT control means, through the second data buffer to the video display logic.