×

d.c. To d.c. voltage regulator having an input protection circuit, a d.c. to d.c. inverter, a saturable reactor regulator, and main and auxiliary rectifying and filtering circuits

  • US 4,462,069 A
  • Filed: 08/14/1981
  • Issued: 07/24/1984
  • Est. Priority Date: 08/14/1981
  • Status: Expired due to Term
First Claim
Patent Images

1. A d.c. to d.c. voltage regulator comprising, a pair of input terminals connectable to a source of d.c. voltage, a protection circuit including transient suppressing means connected to said pair of input terminals, a d.c. to a.c. inverting circuit connected to the output of said protection circuit, said d.c. to a.c. inverting circuit producing a.c. signals which are transformer coupled to the input of a saturable reactor regulating circuit, said saturable reactor regulating circuit having its output coupled to a pair of main output terminals by a rectifying circuit and coupled to a plurality of auxiliary output terminals by a transformer rectifying circuit, and said saturable reactor regulating circuit having a sampling circuit coupled to said pair of main output terminals for sensing the output voltage and for controlling said saturable reactor regulating circuit whereby the output voltage across said pair of main output terminals as well as the output voltages across the plurality of auxiliary output terminals are maintained at a constant level, and an overvoltage protection circuit including a switching transistor and a two-input OR gate, said two-input OR gate includes a first zener diode and pair of resistors for sensing an overvoltage condition across said pair of input terminals and includes a second zener diode and pair of resistors for sensing an overvoltage condition across said pair of main output terminals and for rendering said switching transistor conductive to energize a circuit breaker which opens electrical contacts connected to said pair of input terminals for deenergizing the d.c. to d.c. voltage regulator when an overvoltage condition exists across said pair of input terminals or exists across said pair of output terminals.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×