Dual channel cardiac pacer isolation circuit

• US 4,462,407 A
• Filed: 05/05/1982
• Issued: 07/31/1984
• Est. Priority Date: 05/05/1982
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Cordis Corporation (Cardinal Health, Inc.)
• Inventors: Tarjan, Peter P., Herscovici, Hari
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): Shein, Mitchell J.
• Application Number:
  US06/375,040
• Time in Patent Office: 818 Days
• Field of Search: 128/419 PG, 128/419 PS, 128/419 P
• US Class Current: 607/9
• CPC Class Codes: A61N 1/368 comprising more than one electrode co-operating with different heart regions A61N1/3622, A61N1/3627 take precedence

Abstract

To prevent crosstalk between atrial and ventricular bipolar cardiac pacer leads, separate input/output circuits for the two channels are powered by respective isolated capacitors. In one embodiment, the capacitors are resistively coupled to the pacer battery for continuous charging. In another embodiment, one side of each capacitor is normally disconnected from the pacer battery. Charging switches momentarily connect one or the other capacitor directly to the battery in response to the output of the corresponding sense amplifier.

Claims

1. A cardiac pacer of the type comprising a main power supply, two pacer leads for establishing electrical contact with different parts of the heart, dual channel input/output circuitry including two sense circuits providing logic outputs indicative of electrical activity associated with the respective leads and two stimulation output circuits responsive to logic commands for applying electrical stimulation pulses to the heart via the respective leads and pacing logic circuitry powered by said main power supply for providing logic commands to said stimulation output circuits and connected to receive the outputs of said sense circuits, wherein the improvement comprises:

means for electrically isolating the input/output circuitry including;

(a) first capacitive means for storing electrical energy connected across said input/output circuitry for one channel to supply power thereto;

(b) second capacitive means for storing electrical energy connected across the input/output circuitry for a second channel, and

(c) means operatively connected to said main power supply for separately charging said first and second capacitive means and for isolating said input/output circuitry for the two channels from each other and from the main power supply, whereby crosstalk between said pacing leads is reduced.

2. The pacer of claim 1, wherein one of said leads is an atrial lead and the other lead is a ventricular lead, the respective sense circuits thus being atrial and ventricular sense circuits, the pacing logic circuitry having atrial and ventricular sense inputs, wherein the improvement further comprises an anti-cross-sensing logic circuit including

latch means connected to be set by the beginning of an output pulse from the ventricular sense circuit,

gate means responsive to the condition of said latch means connected between said atrial sense circuit and the atrial sense input to said pacing logic circuitry to pass the output of said atrial sense circuit thereto only when said latch means is in the reset condition, and

means for resetting said latch means in response to the end of an output pulse from said atrial sense circuit and at the expiration of a predetermined period following the beginning of the last output pulse from the ventricular sense circuit if there is no output from the atrial sense circuit.

3. A cardiac pacer of the type comprising a main power supply, two pacing leads for establishing electrical contact with different parts of the heart, first and second input/output circuits associated respectively with said leads and defining respective channels and having means for producing electrical output stimulation to the heart via the respective lead and for producing a logic signal indicative of electrical activity on said lead and pacing logic circuitry energized directly by said main power supply connected to receive the logic outputs of said first and second input/output circuits for producing logic commands to said input/output circuits causing stimulation outputs therefrom, wherein the improvement comprises:

first and second power supplies for said first and second input/output circuits respectively separate from each other and from said main power supply, and

means for at least periodically charging both said first and second power supplies from said main power supply to restore their energy level,

whereby crosstalk between said leads is reduced.

4. The pacer of claim 3, wherein the improvement further comprises:

said power supplies including respectively first and second capacitive means for storing electrical energy connected across said input/output circuits respectively.

5. The pacer of claim 4, wherein said charging means includes first and second pairs of resistive elements connecting opposite sides of said first and second capacitive means respectively to opposite sides of said main power supply, whereby said capacitive means are continuously charged from said main power supply but isolated from each other by virtue of the interceding resistances.

6. The pacer of claim 5, wherein each of said resistive elements has a resistance value on the order of 15 kilohms.

7. The pacer of claim 6, wherein the capacitance of each said capacitive means is chosen such that the corresponding input/output circuit is capable of producing the maximum current output at the maximum desired rate.

8. The pacer of claim 5, wherein the improvement further comprises logic means connected between one of the input/output circuits and said pacing logic circuitry for blocking the sense logic output from said one input/output circuit in the presence of a sense logic output from the other input/output circuit.

9. The pacer of claim 4, wherein said charging means includes first and second pairs of electrical switches arranged to connect opposite sides of the respective capacitive means to said main power supply.

10. The pacer of claim 9, wherein said improvement further comprises:

electronic means for intermittently actuating said first and second pairs of switches to connect said capacitive means momemtarily to said main power supply for recharging.

11. The pacer of claim 10, wherein said actuating means includes first means responsive to the logic output of one input/output circuit for closing a corresponding pair of switches for a predetermined time interval.

12. The pacer of claim 11, wherein said actuating means includes second means responsive to the logic output of the other one of said input/output circuits for closing the other pair of said switches for a predetermined interval.

13. The pacer of claim 9, wherein the improvement further comprises:

a pair of resistive means connected from one side of each of said capacitive elements respectively to the reference potential side of said main power supply in parallel with the corresponding switch.

14. The pacer of claim 13, wherein the improvement further comprises a pair of switch means in series with said resistive elements, respectively, for interrupting the connection to the reference potential side of said power supply whenever the capacitive means for the opposite channel is charging.

15. The pacer of claim 4, wherein said charging means includes first and second pairs of switches for connecting respective sides of said first and second capacitive means to corresponding sides of said main power supply, and means for intermittently actuating at least one of said pairs of switches at a time for a predetermined interval to charge the respective capacitive means.

16. The pacer of claim 15, wherein said improvement further comprises means for referencing the logic level associated with each of said input/output circuits to the reference potential of said main power supply.

17. The pacer of claim 15, wherein said referencing means includes resistive elements connected in parallel with the corresponding switch connecting the respective capacitive element to the reference potential side of said main power supply.

18. The pacer of claim 15, wherein said charging means includes means responsive to a logic output from one of said input/output circuits for actuating a corresponding pair of said switches for a predetermined interval of time to charge the corresponding capacitive means.

19. The pacer of claim 15, wherein said charging means includes a pair of charging logic circuit means each responsive to a sense logic output from a corresponding input/output circuit for actuating a corresponding pair of switches after a predetermined delay for a predetermined interval of time following which said charging logic circuit means is refractory for a predetermined interval.

20. The pacer of claim 15, wherein the improvement further comprises logic means connected between one of the input/output circuits and said pacing logic circuitry for blocking the sense logic output from said one input/output circuit in the presence of a sense logic output from the other input/output circuit.

21. Anti-cross-sensing circuitry for a cardiac pacer having atrial and ventricular leads, means for applying stimulation pulses via said leads, atrial and ventricular sense circuits producing a digital output pulse in response to defined electrical activity on the respective lead, and pacing logic circuitry having atrial and ventricular sense inputs connected to said sense circuits for issuing appropriate stimulation commands for cardiac pacing, comprising

latch means connected to be set by the beginning of an output pulse from the ventricular sense circuit,

gate means responsive to the condition of said latch means connected between said atrial sense circuit and the atrial sense input to said pacing logic circuitry to pass the output of said atrial sense circuit thereto only when said latch means is in the reset condition, and

means for resetting said latch means in response to the end of an output pulse from said atrial sense circuit and at the expiration of a predetermined period following the beginning of the last output pulse from the ventricular sense circuit if there is no output from the atrial sense circuit.