System clock generator in integrated circuit

• US 4,463,440 A
• Filed: 04/15/1981
• Issued: 07/31/1984
• Est. Priority Date: 04/15/1980
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Inoue, Kazuo, Nishiura, Yoshikazu, Mineyama, Takitsugu
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Niessen, William G.
• Application Number:
  US06/254,543
• Time in Patent Office: 1,203 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/143, 307/269, 307/409, 328/62
• US Class Current: 713/400
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H03K 3/03 Astable circuits

Abstract

A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction; and a clock generator supplied with the output of an oscillator for developing a basic clock of a desired waveform for supply to the system, wherein the basic clock is developed or inhibited when the control signal is supplied from the clock control signal generator.

Claims

1. A system clock generator comprising:

clock signal generating means for developing a plurality of sequentially phase shifted clock pulses;

logic means responsive to said clock signal generating means for developing system clock output signals from said sequentially phase shifted clock pulses;

clock control signal generator means operatively connected to said clock signal generating means and said logic means for developing a clock inhibit signal for inhibiting operation of said clock signal generating means and for developing a system clock output signal inhibit signal;

disable means for inhibiting application of said system clock output signals to an output when said system clock output signal inhibit signal is developed by said clock control generation means;

said clock control signal generator means including;

first means for developing said clock inhibit signal,

second means responsive to said first means for developing said system clock output signal inhibit signal, the development of said clock inhibit signal by said first means being terminated in response to a start signal applied thereto,

said second means terminating development of said system clock output signal inhibit signal only when development of said clock inhibit signal has been terminated by said first means and said second means has detected development of a selected one of said system clock output signal to thereby syncronize timing of said clock pulse and system clock output signals.