Burst signal transmission system

• US 4,464,765 A
• Filed: 04/13/1982
• Issued: 08/07/1984
• Est. Priority Date: 04/15/1981
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited 33-1 Shiba Gochome Minato-Ku Tokyo Japan
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Shimizu, Hiroshi
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/368,235
• Time in Patent Office: 847 Days
• Field of Search: 371/40, 371/45, 371/56, 178/69 D, 375/17, 375/19, 375/25, 375/34, 375/58, 455/64, 455/65, 455/63, 370/24, 370/29, 370/32, 375/36
• US Class Current: 375/292
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 5/16 Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Abstract

In a multi-level transmission system, a binary digital signal is converted into a multi-level signal by generating successive multi-level symbols each having a polarity opposite the polarity of the average DC level of preceding symbols, with the first symbol having a first polarity when the first binary bit is a logical "0" and having a second polarity when the first bit is a logical "1". If desired, the logical values of all bits after the first bit can be complemented prior to generating the appropriate multi-level symbols.

Claims

1. In a method of communication of the type comprising the steps of encoding an input digital signal given in a burst mode, representing information and having a plurality of bits including a first bit and succeeding bits each representing either a logical "0" or a logical "1", said input digital signal being encoded into a multi-level signal having a plurality of multi-level symbols including first symbol and succeeding symbols, said plurality of symbols including first polarity symbols, second polarity symbols and zero level symbols, transmitting said multi-level signal and, at a receiving end, decoding said encoded signal to obtain said information, the improvement characterized in that said encoding step comprises:

successively generating said plurality of symbols corresponding to said plurality of bits, including generating a first polarity symbol as said first symbol if said first bit represents a logical "1" and generating a second polarity symbol as said first symbol if said first bit represents a logical "0", each non-zero generated succeeding symbol having a polarity opposite the polarity of the average DC level of prior generated symbols, unless said average DC level is substantially zero in which case the polarity of a non-zero generated symbol is opposite the polarity of the most recent preceding non-zero generated symbol.

2. A method as claimed in claim 1, wherein, when said first bit represents a logical "0", said successively generating step further comprises converting said first bit to a converted bit representing a logical "1" prior to generating said second polarity symbol, and then generating as said first symbol a second polarity symbol in accordance with the information represented by said converted first bit.

3. A method as claimed in claim 1, further comprising at said receiving end the step of extracting a burst synchronization signal from said first symbol of the encoded signal.

4. A method as claimed in claim 2, wherein said decoding step at said receiving end comprises:

converting each symbol of said multi-level signal into a digital signal in accordance with its absolute value to obtain a recovered digital signal having a first bit, and

decoding said first bit of said recovered digital signal as a logical "1" when said first symbol is of said first polarity and decoding said first bit of said recovered digital signal as a logical "0" when said first symbol is of said second polarity.

5. A method as claimed in claim 1, wherein, when said first bit represents a logical "0", said successively generating step further comprises the step of converting each of said succeeding bits to its logical complement to obtain an inverted digital signal prior to generating said plurality of symbols, and then generating said plurality of symbols in accordance with said inverted digital signal.

6. A method as claimed in claim 1, wherein, when said first bit represents a logical "0", said successively generating step further comprises the step of converting each of said succeeding bits to its logical complement to obtain an inverted digital signal prior to generating said plurality of symbols, and then generating said plurality of symbols in accordance with said inverted digital signal;

said decoding step at said receiving end comprising;

converting each multi-level symbol into a digital signal in accordance with its absolute value to obtain a recovered digital signal having a first bit and succeeding bits;

decoding said first bit of said recovered digital signal as a logical "1" when said first symbol is of a first polarity and decoding said first bit of said recovered digital signal as a logical "0" when said first symbol is of said second polarity; and

inverting each of said succeeding bits of said recovered digital signal to its logical complement when said first symbol is of said second polarity.

7. A method as claimed in any one of claims 1-6, wherein each of said multi-level symbols corresponds to a plurality of said input-signal bits.

8. A method as claimed in any one of claims 1, 3 or 5, in which said multi-level symbols comprise three-level symbols which are a positive pulse, a negative pulse, and a zero level.

9. In a communications system of the type including encoding means at a transmitter for encoding an input digital signal, said input digital signal representing information and having a plurality of bits including a first bit and succeeding bits each representing either a logical "0" or a logical "1", said input digital signal being encoded into a multi-level signal having a plurality of multi-level symbols including a first symbol and succeeding symbols, said plurality of symbols including first polarity symbols, second polarity symbols and zero level symbols, transmitting means for transmitting said multi-level signal and, at a receiver, decoding means for decoding said encoded signal to obtain said information, the improvement characterized in that said encoding means comprises:

a first bit detector for detecting whether the first bit of said first input digital signal represents a logical "0" or a logical "1"; and

generating means for successively generating said plurality of symbols corresponding to said plurality of bits, with each generated succeeding non-zero symbol having a polarity opposite the polarity of the average DC level of prior generated symbols, unless said average DC level is substantially zero in which case the polarity of a non-zero generated symbol is opposite the most recent preceding non-zero generated symbol, said generating means, in response to the detection by said first bit detector, generating a first polarity symbol as said first symbol if said first bit represents a logical "1" and generating a second polarity symbol as said first symbol if said first bit represents a logical "0".

10. A system as claimed in claim 9, wherein said generating means includes means for generating a symbol having an absolute value corresponding to a segment of said input digital signal including at least said first bit, and means for assigning a polarity to said absolute value in accordance with an output from said first bit detector.

11. A system as claimed in claim 10, wherein said encoding means further comprises selectable inversion means for inverting said first bit of said input digital signal to obtain an inverted first bit when said first bit of said input digital signal represents a logical "0", said absolute value generating means generating said absolute value in accordance with at least said inverted first bit.

12. A system as claimed in claim 9, wherein said receiver further comprises a first symbol extractor for extracting the polarity of said first symbol and a burst synchronization signal from said encoded signal.

13. A system as claimed in claim 11, wherein said decoding means comprises:

converting means for converting each symbol of said multi-level signal into a digital signal in accordance with its absolute value to obtain a recovered digital signal having a first bit, and

decoding means for decoding said first bit of said recovered digital signal as a logical "1" when said first symbol is of said first polarity and decoding said first bit of said recovered digital signal as a logical "0" when said first symbol is of said second polarity.

14. A system as claimed in claim 13, wherein said selectable inversion means converts each of said succeeding bits to its logical complement when said first bit of said input digital signal represents a logical "0", to thereby obtain an inverted digital signal, said absolute value generating means generating said absolute values in accordance with said inverted digital signal.

15. A system as claimed in claim 14, wherein said decoding means comprises:

converting means for converting each multi-level symbol into a digital signal in accordance with its absolute value to obtain a recovered digital signal having a first bit and succeeding bits;

decoding means for decoding said first bit of said recovered digital signal as a logical "1" when said first symbol is of a first polarity and decoding said first bit of said recovered digital input as a logical "0" when said first symbol is of said second polarity; and

means for inverting each of said succeeding bits of said recovered digital signal to its logical complement when said first symbol is of said second polarity.

16. A system as claimed in any one of claims 9-15, wherein each of said multi-level symbols generated by said generating means corresponds to a plurality of said input signal bits.

17. A system as claimed in any one of claims 9, 10 or 12, in which said multi-level encoder comprises a bipolar encoder for three-level codes which are a positive pulse, a negative pulse, and a zero level, while the multilevel decoder comprises a bipolar decoder.