Phase-locked loop circuit arrangement

• US 4,464,771 A
• Filed: 04/02/1982
• Issued: 08/07/1984
• Est. Priority Date: 04/02/1982
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sorensen, Bendt H.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Watkins, Albert W.
• Application Number:
  US06/364,956
• Time in Patent Office: 858 Days
• Field of Search: 375/120, 375/119, 375/80-82, 360/41, 360/51, 307/511, 307/514, 307/516, 307/518, 307/526-528, 307/262, 307/269, 328/109, 328/110, 328/133, 328/134, 328/155, 328/63, 329/50, 331/1 A, 331/11, 331/12
• US Class Current: 375/374
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another.

A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited.

The invention is particularly applicable to teletext receivers.

Claims

1. A phase locked loop circuit arrangement for synchronizing an oscillator to a NRZ (Non-Return-to-Zero) data signal in which a transition from one potential level to another represents a data transition from one binary value to another;

the arrangement including a controllable oscillator for providing a clock signal;

a phase comparator for comparing the phases of the data and clock signals with one another;

means for applying a control signal to adjust the oscillating frequency of the oscillator in dependence upon an amount by which the phase of the data leads that of the clock signal and vice-versa, the means for applying a control signal including means for inhibiting the application of a control signal to the oscillator during a cycle of the clock signal in which the phase of the clock signal leads that of the data and no data transition occurs, the phase comparator has a first output for providing an output signal indicative of the phase of the data leading that of the clock signal and a second output for providing an output signal indicative of the phase of the clock signal leading that of the data, the means for inhibiting the application of a control signal to the oscillator includes gating means coupled to the second output of the phase comparator and arranged to be enabled by a data transition, and the gating means is coupled to the second output of the phase comparator via a delay circuit which stores an output signal fed from the phase comparator and indicative of the phase of the clock signal leading that of the data during a clock cycle and which feeds to the gating means a signal representative of the phase difference between the clock and data signals following the arrival of a data transition during that clock cycle.

2. A phase-locked loop circuit arrangement as claimed in claim 1, wherein the storage circuit includes capacitive means arranged to be charged at the beginning of a clock cycle in which the phase of the clock signal leads that of the data and to be discharged on arrival during that cycle of a data transition, the charge on the capacitor on the arrival of the data transition being proportional to the time elapsed between the beginning of the clock cycle and the data transition.

3. A phase-locked loop circuit arrangement as claimed in claim 2, wherein the delay circuit includes a comparator having a first input coupled to the capacitive means and a second input coupled to a source of a reference potential, the comparator having an output coupled to the gating means.

4. A phase-locked loop circuit arrangement as claimed in claim 1, or claim 2 wherein means is provided for discharging the capacitive means at the end of a clock cycle in which the phase of the clock signal leads that of the data and in which no data transition occurs.