Phase-locked loop circuit arrangement
First Claim
1. A phase locked loop circuit arrangement for synchronizing an oscillator to a NRZ (Non-Return-to-Zero) data signal in which a transition from one potential level to another represents a data transition from one binary value to another;
- the arrangement including a controllable oscillator for providing a clock signal;
a phase comparator for comparing the phases of the data and clock signals with one another;
means for applying a control signal to adjust the oscillating frequency of the oscillator in dependence upon an amount by which the phase of the data leads that of the clock signal and vice-versa, the means for applying a control signal including means for inhibiting the application of a control signal to the oscillator during a cycle of the clock signal in which the phase of the clock signal leads that of the data and no data transition occurs, the phase comparator has a first output for providing an output signal indicative of the phase of the data leading that of the clock signal and a second output for providing an output signal indicative of the phase of the clock signal leading that of the data, the means for inhibiting the application of a control signal to the oscillator includes gating means coupled to the second output of the phase comparator and arranged to be enabled by a data transition, and the gating means is coupled to the second output of the phase comparator via a delay circuit which stores an output signal fed from the phase comparator and indicative of the phase of the clock signal leading that of the data during a clock cycle and which feeds to the gating means a signal representative of the phase difference between the clock and data signals following the arrival of a data transition during that clock cycle.
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Accused Products
Abstract
The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another.
A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited.
The invention is particularly applicable to teletext receivers.
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Citations
4 Claims
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1. A phase locked loop circuit arrangement for synchronizing an oscillator to a NRZ (Non-Return-to-Zero) data signal in which a transition from one potential level to another represents a data transition from one binary value to another;
- the arrangement including a controllable oscillator for providing a clock signal;
a phase comparator for comparing the phases of the data and clock signals with one another;
means for applying a control signal to adjust the oscillating frequency of the oscillator in dependence upon an amount by which the phase of the data leads that of the clock signal and vice-versa, the means for applying a control signal including means for inhibiting the application of a control signal to the oscillator during a cycle of the clock signal in which the phase of the clock signal leads that of the data and no data transition occurs, the phase comparator has a first output for providing an output signal indicative of the phase of the data leading that of the clock signal and a second output for providing an output signal indicative of the phase of the clock signal leading that of the data, the means for inhibiting the application of a control signal to the oscillator includes gating means coupled to the second output of the phase comparator and arranged to be enabled by a data transition, and the gating means is coupled to the second output of the phase comparator via a delay circuit which stores an output signal fed from the phase comparator and indicative of the phase of the clock signal leading that of the data during a clock cycle and which feeds to the gating means a signal representative of the phase difference between the clock and data signals following the arrival of a data transition during that clock cycle. - View Dependent Claims (2, 3, 4)
- the arrangement including a controllable oscillator for providing a clock signal;
Specification