Method for fabricating MOS device with self-aligned contacts

• US 4,466,172 A
• Filed: 07/27/1981
• Issued: 08/21/1984
• Est. Priority Date: 01/08/1979
• Status: Expired due to Term

• Current Assignee: AMI Semiconductor Inc (ON Semiconductor Corporation)
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Batra, Tarsaim L.
• Primary Examiner(s): Saba, W. G.
• Application Number:
  US06/287,388
• Time in Patent Office: 1,121 Days
• Field of Search: 29/571, 29/578, 29/576 B, 29/589, 29/590, 148/1.5, 148/187, 156/653, 156/657, 156/662, 357/235, 357/41, 357/59
• US Class Current: 438/287
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/76216 introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) surrounding openings (99) therein for the MOSFET elements. A gate electrode (38) within each opening is utilized to provide self-registered source (42) and drain (44) regions and is covered on all sides and on its top surface with a gate dielectric layer (46). After the formation of the source-drain regions a relatively thin dielectric protective layer (38) is applied to the entire chip prior to the application of an upper insulative layer (50). When oversized windows are etched in the upper insulative layer, the protective layer prevents etching of the gate dielectric layer (46), thus preventing shorts or leaks between conductive and active areas and providing self-aligned contacts with minimum spacing from adjacent conductive areas (40). With the present method, additional internal protection over prior art devices is provided in MOS devices with source-drain regions formed either by diffusion or ion implantation.

Claims

1. A method for fabricating an integrated circuit semiconductor device having a plurality of field effect transistor (FET) elements with self-registering electrical contacts on their source and drain regions and their gate electrodes connected to the device interconnection lines, said method comprising the steps of:

forming a patterned layer of field oxide on a semiconductive substrate of a first conductivity type in order to form active areas free from said field oxide on the substrate surface for the formation of said FET elements;

forming a relatively thin gate dielectric layer within said active areas;

forming a layer of conductive material over the surface of the substrate;

patterning said layer of conductive material into conductive gate electrodes of a predetermined shape and thickness, over said gate dielectric layer within said open areas;

forming a first layer of dielectric material on the sides and top of each said conductive gate electrodes;

forming, within each said active area surrounded by said field oxide, doped silicon source and drain regions of a second conductivity type material opposite to said first conductivity type of said substrate, the boundaries of said source and drain regions being determined by the edge of said field oxide and by the edges of said gate electrodes whereby said source and drain regions are self-aligned with respect to the edges of said gate electrode;

forming a relatively thin layer of protective material over the entire device including all areas of conductive material in said active areas and said field oxide areas;

covering said thin layer of protective material on said device with a relatively thick layer of insulating material;

forming oversized contact openings through said insulating material over said gate electrode and over said source and drain regions where electrical contacts are to be formed;

removing said second layer of dielectric material within said oversized contact openings;

removing said gate oxide from the surfaces of said source and drain regions with said oversized contact openings; and

depositing a metallic-type, high-electrical conductivity interconnection line pattern on the surface of the wafer extending into said contact openings thereby forming electrical connections with said source and drain regions within said contact openings.

2. The method as described in claim 1 wherein said layer of protective material is silicon nitride formed to a thickness in the range of 100 Å

to 300 Å

.

3. The method as described in claim 2 wherein the upper surface of said silicon nitride protective layer is oxidized before application of said insulating material.

4. The method as described in claim 1 wherein said protective layer is silicon carbide.

5. The method as described in claim 1 wherein said protective layer is aluminum oxide.

6. The method as described in claim 1 wherein said gate dielectric layer is a sandwich of silicon nitride over silicon dioxide.

7. The method as described in claim 1 wherein said conductive gate electrodes are polycrystalline silicon and said first layer of dielectric material on the sides and top of each said conductive gate electrodes is silicon dioxide.

8. The method as described in claim 7 wherein said source and drain regions are formed by ion implantation.

9. The method as described in claim 1 wherein said first layer of silicon dioxide on said gate electrodes has a thickness of around 3000 Å

to 5000 Å

.

10. The method as described in claim 1 wherein said conductive gate electrodes are polycrystalline silicon whose sides are covered with a layer of silicon dioxide and whose top is covered with a layer of silicon nitride.

11. The method as described in claim 10 wherein the thickness of the silicon dioxide layer on the sides of said gate electrode is around 3000 Å

to 5000 Å and

wherein the thickness of said silicon nitride layer on the top thereof is around 1000 Å

to 2000 Å

.

12. The method as described in claim 10 wherein said source and drain regions for each said FET are formed by a diffusion process.