Generalized interpolative method for digital/analog conversion of PCM signals

• US 4,467,316 A
• Filed: 06/03/1981
• Issued: 08/21/1984
• Est. Priority Date: 06/03/1980
• Status: Expired due to Fees

• Current Assignee: Licentia Patent-Verwaltungs-GmbH (AB Electrolux)
• Original Assignee: Licentia Patent-Verwaltungs-GmbH (AB Electrolux)
• Inventors: Musmann, Hans-Georg, Korte, Wilhelm W.
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/269,942
• Time in Patent Office: 1,175 Days
• Field of Search: 375/27, 375/26, 375/94, 364/724, 340/347 DA
• US Class Current: 341/144
• CPC Class Codes: H03M 1/72 Sequential conversion in series-connected stages H03M1/68 takes precedence

Abstract

A method for effecting digital to analog conversion of PCM signals by a generalized interpolative procedure, by sampling the PCM signals at a first sampling rate and supplying each sampled word in succession to a first input of a digital adder; dividing each word at the output of the adder into a first part representing the higher value portion of the adder output word and having a length shorter than that of the adder input word, and a second part representing the lower value part of the adder output word; conducting the second part of each adder output word through a digital, nonrecursive counter feedback filter having a degree greater than one at a clock pulse rate which is an integral multiple of the sampling rate, and supplying each resulting word at the filter output to a second input of the digital adder where it is added to the stored word at the first adder input; converting the first part of each adder output word into an analog signal in a digital/analog converter having a small number of available output values; and passing the analog signal at the output of the converter through an analog lowpass filter.

Claims

1. A method for effecting digital to analog conversion of PCM signals by a generalized interpolative procedure, comprising the steps of:

sampling the PCM signals at a first sampling rate and effecting intermediate storage of each sampled PCM signal word in succession;

supplying each stored word in succession to a first input of a first digital adder;

dividing each word at the output of the adder into a first part representing the higher value portion of the adder output word and having a length shorter than that of the adder input word, and a second part representing the lower value part of the adder output word;

conducting the second part of each adder output word through a digital, nonrecursive counter feedback filter having a degree greater than one at a clock pulse rate which is an integral multiple of the sampling rate, and supplying each resulting word at the filter output to a second input of the first digital adder where it is added to the stored word at the first adder input;

transferring the first part of each adder output word at the clock pulse rate to a system output;

setting the degree and pulse response of the filter to values minimizing the quantizing error, due to the difference in length and value between each adder output word first part and the corresponding sampled signal word, within the useful frequency band of the resulting signal in such a manner as to cause the power content of the quantizing error in that band to be negligible compared to the quantizing error power contained in the PCM signals;

converting the successive adder output word first parts at the system output into an analog signal to a digital/analog converter having a small number of available output values; and

passing the analog signal at the output of the converter through an analog lowpass filter for suppressing periodic continuations of the useful signal frequency band created by the sampling and for sufficiently attenuating the additional concentrated quantizing distortions due to the length of the adder output word first part being shorter than that of the word at the adder first input, wherein said step of conducting comprises;

storing in respective locations of a fixed value memory representations of the filter coefficients;

feeding the second part of each adder output word through a shift register chain having taps which are connected to the address input of the fixed value memory, the taps being so arranged that at each of them there appears one identical-value bit of the output word second parts;

reading the representations out of one of the memory locations together with the bit pattern present at the shift register chain taps;

summing the read out representations in an accumulative circuit connected between the output of the memory and the second digital adder input in such a manner that after a number of clock pulses corresponding to the length of each adder output word second part, a new word appears at the accumulator circuit output.

2. A method for effecting digital to analog conversion of PCM signals by a generalized interpolative procedure, comprising the steps of:

sampling the PCM signals at a first sampling rate and effecting intermediate storage of each sampled PCM signal word in succession;

supplying each stored word in succession to a first input of a first digital adder;

dividing each word at the output of the adder into a first part representing the higher value portion of the adder output word and having a length shorter than that of the adder input word, and a second part representing the lower value part of the adder output word;

conducting the second part of each adder output word through a digital, nonrecursive counter feedback filter having a degree greater than one at a clock pulse rate which is an integral multiple of the sampling rate, and supplying each resulting word at the filter output to a second input of the first digital adder where it is added to the stored word at the first adder input;

transferring the first part of each adder output word at the clock pulse rate to a system output;

setting the degree and pulse response of the filter to values minimizing the quantizing error, due to the difference in length and value between each adder output word first part and the corresponding sampled signal word, within the useful frequency band of the resulting signal in such a manner as to cause the power content of the quantizing error in that band to be negligible compared to the quantizing error power contained in the PCM signals;

converting the successive adder output word first parts at the system output into an analog signal in a digital/analog converter having a small number of available output values; and

passing the analog signal at the output of the converter through an analog lowpass filter for suppressing periodic continuations of the useful signal frequency band created by the sampling and for sufficiently attenuating the additional concentrated quantizing distortions due to the length of the adder output word first part being shorter than that of the word at the adder first input, wherein said step of converting comprises subjecting each adder output first part to at least one further reduction of length in at least one further interpolative network, the last of which networks includes a second digital adder having one input connected to receive the higher value part of each word produced by the preceding network, and a digital accumulator connected in feedback between the output of the second adder and a second input of the second adder, said step of subjecting including passing the lower value part of each word at the output of the second adder through the accumulator at a second clock pulse rate higher than the first-recited clock pulse rate and conducting only the highest order bit of each word at the output of the second adder to the digital/analog converter, and wherein the digital/analog converter has only two available output values.

4. A method as defined in claim 2 or 3, wherein said step of conducting comprises:

storing in respective locations of a fixed value memory representations of the filter coefficients;

feeding the second part of each adder output word through a shift register chain having taps which are connected to the address input of the fixed value memory, the taps being so arranged that at each of them there appears one identical-value bit of the output word second parts;

reading the representations out of one of the memory locations together with the bit pattern present at the shift register chain taps;

summing the read out representations in an accumulative circuit connected between the output of the memory and the second digital adder input in such a manner that after a number of clock pulses corresponding to the length of each adder output word second part, a new word appears at the accumulator circuit output.

3. A method for effecting digital to analog conversion of PCM signals by a generalized interpolative procedure, comprising the steps of:

sampling the PCM signals at a first sampling rate and effecting intermediate storage of each sampled PCM signal word in succession;

supplying each stored word in succession to a first input of a first digital adder;

dividing each word at the output of the adder into a first part representing the higher value portion of the adder output word and having a length shorter than that of the adder input word, and a second part representing the lower value part of the adder output word;

conducting the second part of each adder output word through a digital, nonrecursive counter feedback filter having a degree greater than one at a clock pulse rate which is an integral multiple of the sampling rate, and supplying each resulting word at the filter output to a second input of the first digital adder where it is added to the stored word at the first adder input;

transferring the first part of each adder output word at the clock pulse rate to a system output;

setting the degree and pulse response of the filter to values minimizing the quantizing error, due to the difference in length and value between each adder output word first part and the corresponding sampled signal word, within the useful frequency band of the resulting signal in such a manner as to cause the power content of the quantizing error in that band to be negligible compared to the quantizing error power contained in the PCM signals;

converting the successive adder output word first parts at the system output into an analog signal in a digital/analog converter having a small number of available output values; and

passing the analog signal at the output of the converter through an analog lowpass filter for suppressing periodic continuations of the useful signal frequency band created by the sampling and for sufficiently attenuating the additional concentrated quantizing distortions due to the length of the adder output word first part being shorter than that of the word at the adder first input, wherein said step of converting comprises subjecting each adder output first part to at least one further reduction of length in at least one further interpolative network, the last of which networks includes a read-only memory containing, in respective locations, all possible bit serial patterns corresponding to all possible values of the higher value part of each word produced by the preceding network, and said step of subjecting includes addressing the memory with the higher value part of each work produced by the preceding network, transferring the bit serial pattern at the addressed location into a register and reading that pattern out of the register serially to the digital/analog converter, and wherein the digital/analog converter has only two available output values.