Multi-phase subroutine control circuitry

• US 4,467,410 A
• Filed: 02/04/1981
• Issued: 08/21/1984
• Est. Priority Date: 02/04/1981
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Corp (Unisys Corporation)
• Inventors: Kim, Dongsung R.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/231,554
• Time in Patent Office: 1,294 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 718/100
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address

Abstract

Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subrouting control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

Claims

1. A method of subroutine control in a data processing system which operates by performing a plurality of tasks wherein a task may include one or more subroutines, said method comprising the steps of:

providing subroutine entry and task identification indications when a performing task arrives at the beginning of a subroutine;

providing subroutine return and task identification indications when a performing task arrives at the end of a subroutine;

determining a return address in response to said subroutine entry indication;

storing the determined return address in a first return address storage means corresponding to the identified task;

also storing the most recently determined return address for each task in a second return address storage means corresponding to the indentified task, said second return address storage means providing for significantly faster access than said first return address storage means; and

accessing in response to said subroutine return indication the most recent return address stored in the second return address storage means of the identified task for transfer to said system and then replacing with the next most recent address from the first storage means of the identified task; and

performing the aforementioned steps of storing, accessing and determining concurrently for different tasks.

2. The invention in accordance with claim 1, wherein said system operates cyclically, and wherein the steps of storing, accessing and determining are staged to occur over a plurality of cycles in a manner so as to provide phased subroutine control for a plurality of concurrently performing tasks.

3. In a cyclically operating data processing system which provides for the concurrent performance of a plurality of tasks wherein a task may include one or more subroutines, subroutine control means comprising:

a return address storage means, one for each task, for storing return addresses for the respective task during performance thereof; and

return address control means responsive to a subroutine entry indication and a task identification indication provided by said system when a task enters a subroutine for determining a return address for the indicated subroutine and for storing said return address in the return address storage means of the respective task;

said return address control means also being responsive to a subroutine entry return indication and a task identification indication provided by said system when a task arrives at the end of a routine for causing a particular return address stored in the respective storage means of the identified task to be accessed therefrom and applied to said system;

said return address control means operating during a cycle to permit a return address to be determined for a first task concurrently with the storing of a return address for a second task in its respective return address storage means, and also concurrently with the accessing of a return address for a third task from its respective return address storage means for transfer to said system;

said return address storage means including a first storage means for each task for storing a plurality of return addresses for its respective task and a second significantly faster storage means for each task for storing the most recent address of its respective task;

said return address control means operating during a cycle in response to said subroutine entry and task identification indications for causing the determined return address to be stored in both of the respective first and second storage means of the identified task;

said return address control means operating during a cycle in response to said subroutine return and task identification indications to access the most recent return address from the second storage means of the identified task for transfer to said system;

said return address control means also operating during said cycle in response to said subroutine return and task identification indications for causing the next most recent return address to be accessed from the respective first storage means of the identified task and to be stored in the second storage means of the identified task.

4. The invention in accordance with claim 3, wherein the first storage means of each task comprises a stack for storing a plurality of return addresses, wherein a stack level pointer register is provided for each stack for storing a stack level pointer indicative of the number of return addresses stored in its respective stack, wherein the second return address storage means of each task comprises a fast access register, wherein said control means operates to store a return address in a stack at a level indicated by its respective stack level pointer, wherein said control means operates in response to said entry and return indications to maintain the stack level pointers correctly updated, and wherein said control means accesses the next most recent return address from a stack at the level indicated by the respective stack level pointer.

5. The invention in accordance with claim 4, wherein said return address control means includes means responsive to a task identification indication provided by said system for accessing from the respective stack level pointer register the respective stack level pointer value for the identified task for use by said control means in storing a return address at the appropriate level of the stack corresponding to the identified task.