Slave processor with clock controlled by internal ROM & master processor

• US 4,467,412 A
• Filed: 05/18/1981
• Issued: 08/21/1984
• Est. Priority Date: 05/18/1981
• Status: Expired due to Fees

• Current Assignee: Atari Incorporated (Infogrames Entertainment SA)
• Original Assignee: Atari Incorporated (Infogrames Entertainment SA)
• Inventors: Hoff, Morgan P.
• Primary Examiner(s): Krass, Errol A.
• Assistant Examiner(s): Williams, Jr, Archie E.
• Application Number:
  US06/264,261
• Time in Patent Office: 1,191 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/ 131-132, 364/136, 364/731, 364/521-522, 364/410, 340/723-729, 273/85 G, 273/135 A, 273/DIG. 28
• US Class Current: 710/110
• CPC Class Codes: A63F 13/52 involving aspects of the displayed game scene
• CPC Class Codes: A63F 13/5252 using two or more virtual cameras concurrently or sequentially, e.g. automatically switching between fixed virtual cameras when a character changes room or displaying a rear-mirror view in a car-driving game
• CPC Class Codes: A63F 13/57 Simulating properties, behaviour or motion of objects in the game world, e.g. computing tyre load in a car race game A63F13/56 takes precedence
• CPC Class Codes: A63F 2300/64 for computing dynamical parameters of game objects, e.g. motion determination or computation of frictional forces for a virtual car
• CPC Class Codes: A63F 2300/66 for rendering three dimensional images
• CPC Class Codes: A63F 2300/6669 using a plurality of virtual cameras concurrently or sequentially, e.g. automatically switching between fixed virtual cameras when a character change rooms
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G09B 9/301 by computer-processed or -generated image

Abstract

A graphical display of a video game is provided with "first person views" of game play, by generation of simulated three-dimensional perspectives. A slave computational unit relieves a master microprocessor of arithmetic and logical operations necessary for coordinate transformations required to generate the desired video image vectors. Within the slave unit, decoded addresses from the master unit initiate access of microinstructions, from a ROM, which control a dedicated ALU which performs the transformation calculations. When the tasks are finished, the slave processor'"'"'s clock is turned off by microcode from the slave'"'"'s own ROM. The results of the slave'"'"'s computations are retrieved by the master processor and inserted into vector instructions to drive a CRT.

Claims

1. In a system containing a host processor with a host address bus, a host data bus, and a system clock line, a slave processor and slave address bus comprising:

memory means for storing microinstructions and providing stored microinstructions on a memory output bus in response to addresses presented on said slave address bus, said memory means being a read only memory;

an arithmetic logic unit coupled to at least a portion of said memory output bus, said arithmetic logic unit being adapted to perform arithmetic and logic operations in response to microinstructions provided by said memory means on said memory output bus, said arithmetic logic unit also being coupled to a slave clock line for receiving clock signals;

a sequencer coupled to said slave address bus, said sequencer providing addresses on said slave address bus;

a decoder coupled to said host address bus, said decoder providing a start signal in response to the presence of a predetermined address on said host address bus;

a clock control circuit coupled to said system clock line, said slave clock line, said decoder and at least one output line from said memory means, said clock control circuit sending clock signals on said slave clock line in response to clock signals on said system clock line, terminating the sending of clock signals on said slave clock line in response to the presence of a predetermined condition on said output line, and resuming the sending of clock signals on said slave clock signal line in response to said start signal;

a mapping ROM coupled to said host address bus, said mapping ROM providing an address on a mapping ROM output bus in response to addresses on said host address bus;

a multiplexer coupled to said mapping ROM output bus, said multiplexer providing an output on a multiplexer output bus in response to data on said mapping ROM output bus; and

a load control circuit coupled to said sequencer and said start signal output line, said load control circuit causing the loading by the sequencer of the data on said multiplexer output bus in response to a start signal on said start signal output line.