Robot arm controller with common bus memory

• US 4,467,436 A
• Filed: 10/26/1981
• Issued: 08/21/1984
• Est. Priority Date: 10/26/1981
• Status: Expired due to Fees

• Current Assignee: Dexon, Inc.
• Original Assignee: United States Robots Incorporated
• Inventors: Weiss, Mitchell, Chance, Peter E.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US06/314,914
• Time in Patent Office: 1,030 Days
• Field of Search: 364/200, 364/513
• US Class Current: 700/249
• CPC Class Codes: G05B 19/4141 characterised by a controller or microprocessor per axis
• CPC Class Codes: G05B 2219/33156 Communication between two processors over shared, dualport ram
• CPC Class Codes: G05B 2219/33209 Protocol, mailbox, email, mail system
• CPC Class Codes: G05B 2219/33337 For each axis a processor, microprocessor
• CPC Class Codes: G05B 2219/34044 Mathematical coprocessor - processor
• CPC Class Codes: G05B 2219/34069 Shared memory
• CPC Class Codes: G05B 2219/45083 Manipulators, robot

Abstract

In a robotic apparatus having a manipulator arm including plural motors to move the arm to predetermined spatial positions and a control system for the arm, a common bus and common memory connected to the bus. The control system comprises respective microprocessor based controllers for each of the joints, microprocessor based computation means for performing the mathematical computation to control the trajectories of the arm and common microprocessor based coordinating control system for coordinating the activities of the other modular microprocessor based control system. Accessing routine is associated with the bus for providing each of the microprocessor based control system with direct, exclusive access to the bus during respective time intervals. The common memory serves as a depository for messages to and from the microprocessor based control system to enable intercommunication between the microprocessor based control system accessing the bus.

Claims

1. A robot apparatus comprising a manipulator arm having plural joints and respective motor means associated with said joints to move said manipulator arm to a predetermined spatial position and control means for said arm, said control means comprising respective modular microprocessor based control means for the control of said motors, microprocessor based control means for performing the mathematical computations required to control the trajectories of said arm and common modular microprocessor based coordinating control means for coordinating the activities of said other modular microprocessor based control means, a common electrical bus and accessing means including fixed internal timing means for establishing a predetermined timing cycle for accessing said bus, each of said microprocessor based control means being connected to said common bus by said accessing means, all of said microprocessor based control means being arranged to operate in parallel with one another, said accessing means providing each of said microprocessor based control means with direct periodic access to said bus during each timing cycle.

2. The apparatus of claim 1 wherein said bus is arranged to have connected thereto additional components for said apparatus by use of said accessing means.

3. The apparatus of claim 1 additionally comprising common memory means connected to said bus and serving as a depository for messages to and from said microprocessor based control means to enable intercommunication between said microprocessor based control means through said bus and said common memory means.

4. The apparatus of claim 3 wherein said microprocessor based control means which are connected to said bus are given access to said bus in serial sequence.

5. The apparatus of claim 4 wherein said bus is arranged to have connected thereto additional components for said apparatus by use of said accessing means.

6. The apparatus of claim 4 wherein none of said microprocessor based control means has to go into a wait state before having access to said bus.

7. The apparatus of claim 1 wherein said common microprocessor based coordinating control means is arranged to produce signals whenever access is to be given to another microprocessor based control means and wherein said other microprocessor based control means is arranged to produce signals when it desires access to said bus, whereupon said other microprocessor based control means is granted access to said bus by said accessing means.

8. The apparatus of claim 7 additionally comprising common memory means connected to said bus and serving as a depository for messages to and from said microprocessor based control means to enable intercommunication between said microprocess based control means through said bus and said common memory means.

9. The apparatus of claim 8 wherein said microprocessor based control means which are connected to said bus are given access to said bus in serial sequence.

10. The apparatus of claim 9 wherein said bus is to have connected thereto additional components for said apparatus by use of said accessing means.

11. The apparatus of claim 1 wherein said access is exclusive during respective time intervals.

12. The apparatus of claim 11 wherein said time intervals are sequential.