Multi-direction time division multiplex communication system

• US 4,470,141 A
• Filed: 06/06/1979
• Issued: 09/04/1984
• Est. Priority Date: 06/06/1978
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Takada, Masami
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/046,055
• Time in Patent Office: 1,917 Days
• Field of Search: 370/104, 370/50, 370/100, 455/11, 455/12, 455/13, 455/51, 455/54, 375/107
• US Class Current: 370/324
• CPC Class Codes: H04B 7/212 Time-division multiple access [TDMA]
• CPC Class Codes: H04B 7/2125 Synchronisation

Abstract

The inventive system includes a central station and a plurality of satellite stations which communicate on a time division multiplex basis. The central station generates frame synchronizing and clock signals, along with digital communication signals, which are suitably modulated into channel time slots. During its individually assigned channel time slot, each satellite station extracts the frame and clock signals and demodulates the communication signals which were directed to it. The extracted frame and clock signals are used in the satellite station to retime the communication signals which are sent in bursts of modulated carrier waves from the satellite stations to the central station. The central station demodulates the bursts of carrier waves to transmit the intelligence therein to its destination. The advantage is that many stations can share the same frequency and thereby make more efficient use of the transmission capacity.

Claims

1. A multi-direction time division multiplex communication system for communication between a first station with a transmitter/receiver unit and a plurality of second stations, each with a transmitter/receiver unit, wherein:

a. the transmitter of said first station comprises a first means for generating a frame synchronizing signal and a clock signal;

a second means responsive to said frame synchronizing signal, to said clock signal and to a first digital signal for arranging said frame synchronizing signal and said first digital signal in a first channel in a time-division multiplex format;

a third means responsive to a second digital signal for producing a continuous modulated carrier wave; and

a fourth means for transmitting said continuous modulated carrier wave;

b. the receiver of each of said second stations comprising a fifth means responsive to said continuous modulated carrier wave for producing said second digital signal;

a sixth means for extracting said frame synchronizing and clock signals from the output signal of said fifth means; and

a seventh means responsive to the extracted frame synchronizing signal for separating a digital signal within a time period assigned to said second station, said digital signal being separated from the second digital signal and demodulated;

c. the transmitter of each of said second stations comprises an eighth means responsive to the extracted frame synchronizing and clock signals for producing first and second timing signals;

a ninth means responsive to said first and second timing signals and responsive to a third digital signal for arranging said first timing signal and said third digital signal in a second channel in time-division multiplex format, thereby producing a fourth digital signal;

a tenth means responsive to said fourth digital signal for producing a burst modulated carrier wave during only a time period assigned to said second station by said first timing signal; and

an eleventh means for delaying said first timing signal so that the receiver of said first station receives, in a time-division multiplex format and in a predetermined sequential order, a plurality of the burst modulated carrier waves having the same frequencies that are transmitted from transmitters of said second stations; and

d. the receiver of said first station comprises a twelfth means for demodulating the burst modulated carrier waves from said plurality of second stations to produce the plurality of said fourth digital signals;

a thirteenth means responsive to both the frame synchronizing signal and the clock signal from said first means for delaying at least these signals to produce third and fourth timing signals; and

a fourteenth means for converting a plurality of the demodulated fourth digital signals into a fifth digital signal responsive to said third and fourth timing signals.

2. A multi-direction time division multiplex communication system as claimed in claim 1, wherein said eleventh and thirteenth means include delay circuit means for delaying said first timing signal and said frame synchronizing signals up to approximately one half of the period of the frame synchronizing signal, respectively.

3. A multi-direction time division multiplex communication system for communication between a first station with a transmitter/receiver unit and a plurality of second stations, each with a transmitter/receiver unit, wherein:

a. the transmitter of said first station comprises a first means for generating a frame synchronizing signal and a clock signal;

a second means responsive to said frame synchronizing signal, to said clock signal and to a first digital signal for arranging said frame synchronizing signal and said first digital signal in a first channel in a time-division multiplex format;

a third means responsive to a second digital signal for producing a continuous modulated carrier wave; and

a fourth means for transmitting said continuous modulated carrier wave;

b. the receiver of each of said second stations comprising a fifth means responsive to said continuous modulated carrier wave for producing said second digital signal;

said fifth means including a synchronizing detector circuit means with a carrier wave recovering means for demodulating the continuous modulated carrier wave into said second digital signal;

a sixth means for extracting said frame synchronizing and clock signals from the output signal of said fifth means; and

a seventh means responsive to the extracted frame synchronizing signal for separating a digital signal within a time period assigned to said second station, said digital signal being separated from the second digital signal and demodulated;

c. the transmitter of each of said second stations comprises an eighth means responsive to the extracted frame synchronizing and clock signals for producing first and second timing signals;

a ninth means responsive to said first and second timing signals and responsive to a third digital signal for arranging said first timing signal and said third digital signal in a second channel in time-division multiplex format, thereby producing a fourth digital signal;

a tenth means responsive to said fourth digital signal for producing a burst modulated carrier wave during only a time period assigned to said second station by said first timing signal; and

an eleventh means for delaying said first timing signal so that the receiver of said first station receives, in a time-division multiplex format and in a predetermined sequential order, a plurality of the burst modulated carrier waves having the same frequencies that are transmitted from transmitters of said second stations; and

d. the receiver of said first station comprises a twelfth means for demodulating the burst modulated carrier waves from said plurality of second stations to produce the plurality of said fourth digital signals;

a thirteenth means responsive to both the frame synchronizing signal and the clock signal from said first means for delaying at least these signals to produce third and fourth timing signals; and

a fourtheenth means for converting a plurality of the demodulated fourth digital signals into a fifth digital signal responsive to said third and fourth timing signals;

e. said second station further comprises a fifteenth means for frequency-multiplying and dividing the recovered carrier wave derived from said fifth means and the clock signal extracted from said sixth means to produce first and second control signals;

a sixteenth means for synthesizing said first and second control signals to produce third and fourth control signals; and

a seventeenth means for controlling the frequency and the phase of said continuous modulated carrier wave and said burst modulated carrier wave by said third and fourth control signals.

4. A multi-direction time division multiplex communication system comprising a central station and a plurality of satellite stations;

means in said central station for transmitting continuously modulated signals having time slots which are individually assigned to each of said satellite stations, each of said time slot signals including frame, clock and first digital intelligence signals;

means in each of said satellite stations effective during its individually assigned time slot for separating said frame and clock signals from said continuously modulated signals;

means in each of said satellite stations, responsive to said separated signals for retiming and transmitting second digital intelligence signals in the form of bursts of modulated carrier waves, all of said carrier waves having the same frequency;

means in said central station for delaying at least said frame and clock signals; and

means in said central stations, responsive to the delayed frame and clock signals for reproducing said second digital intelligence signals from said bursts of carrier waves.

5. The system of claim 4 wherein said central station has a plurality of antennas, each of said antennas being for communicating with a different plurality of said satellite stations.

6. The system of claim 4 wherein communication paths between said central station and each of said satellite stations may have a different propagation time, and means in said satellite stations for adjusting said retiming as a function of the different propagation times.

7. The system of claim 4 wherein said modulated carrier wave is a phase shifted time division multiplex carrier wave.

8. The system of claim 4 wherein said retiming means includes a delay circuit means for delaying signals up to approximately one-half of a frame.