Planarization of multi-level interconnected metallization system

• US 4,470,874 A
• Filed: 12/15/1983
• Issued: 09/11/1984
• Est. Priority Date: 12/15/1983
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brooks, Garth A., Bartush, Thomas A., Kitcher, James R.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/561,778
• Time in Patent Office: 271 Days
• Field of Search: 156/643, 156/646, 156/651, 156/652, 156/653, 156/657, 156/656, 156/659.1, 156/662, 252/79.1, 427/38, 427/39, 204/19 ZE
• US Class Current: 438/631
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF₄ ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.

Claims

1. A method for fabricating interconnection stud structures on a substrate having formed on an insulated surface thereof a conductive metallic pattern interconnected to internal circuits in said substrate through via openings in said surface comprising:

(A) forming at least one conductive vertical stud on said surface;

(B) blanket depositing a dielectric layer on said surface to imbed said pattern and said stud;

(C) blanket coating a resist layer on said dielectric layer;

(D) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric and resist layers, and continuing said etching to remove said resist layer concurrently with planarization of said dielectric layer; and

(E) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric layer and said studs, and continuing second said etching to expose the top surface of each said stud in a substantially common plane with said dielectric layer.

2. The method of claim 1 wherein Step A comprises the formation of at least two of said studs having the top surfaces thereof extending in respective vertically displaced planes relative to said surface.

3. The method of claim 2 wherein said dielectric comprises quartz, and said pattern and each of said studs comprise on aluminum-based alloy.

4. The method of claim 3 including the step of blanket coating said substrate pattern and each said stud with silicon nitirde between Steps A and B.

5. The method of claim 1 wherein said dielectric comprises quartz, and said pattern and each of said studs comprises on aluminum-based alloy.

6. The method of claim 5 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

7. The method of claim 1 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

8. The method of claim 3 wherein the first said etching ambient of step D comprises CF₄.

9. The method of claim 8 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

10. The method of claim 8 wherein the second said ambient of Step E is a noble gas.

11. The method of claim 10 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

12. The method of claim 5 wherein the first said etching ambient of Step D comprises CF₄.

13. The method of claim 12 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

14. The method of claim 12 wherein the second said ambient of Step E is a noble gas.

15. The method of claim 14 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.

16. The method of claim 1 wherein said substrate comprises an integrated circuit device.

17. The method of claim 1 wherein said substrate comprises an integrated circuit device.

18. The method of claim 2 wherein said substrate comprises an integrated circuit device.

19. The method of claim 3 wherein said substrate comprises an integrated circuit device.

20. The method of claim 4 wherein said substrate comprises an integrated circuit device.

21. The method of claim 5 wherein said substrate comprises an integrated circuit device.

22. The method of claim 6 wherein said substrate comprises an integrated circuit device.

23. The method of claim 7 wherein said substrate comprises an integrated circuit device.

24. The method of claim 8 wherein said substrate comprises an integrated circuit device.

25. The method of claim 9 wherein said substrate comprises an integrated circuit device.

26. The method of claim 10 wherein said substrate comprises an integrated circuit device.

27. The method of claim 11 wherein said substrate comprises an integrated circuit device.

28. The method of claim 12 wherein said substrate comprises an integrated circuit device.

29. The method of claim 13 wherein said substrate comprises an integrated circuit device.

30. The method of claim 14 wherein said substrate comprises an integrated circuit device.

31. The method of claim 15 wherein said substrate comprises an integrated circuit device.

32. The method of claim 16 wherein said substrate comprises an integrated circuit device.