Planarization of multi-level interconnected metallization system
First Claim
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1. A method for fabricating interconnection stud structures on a substrate having formed on an insulated surface thereof a conductive metallic pattern interconnected to internal circuits in said substrate through via openings in said surface comprising:
- (A) forming at least one conductive vertical stud on said surface;
(B) blanket depositing a dielectric layer on said surface to imbed said pattern and said stud;
(C) blanket coating a resist layer on said dielectric layer;
(D) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric and resist layers, and continuing said etching to remove said resist layer concurrently with planarization of said dielectric layer; and
(E) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric layer and said studs, and continuing second said etching to expose the top surface of each said stud in a substantially common plane with said dielectric layer.
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Abstract
The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.
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Citations
32 Claims
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1. A method for fabricating interconnection stud structures on a substrate having formed on an insulated surface thereof a conductive metallic pattern interconnected to internal circuits in said substrate through via openings in said surface comprising:
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(A) forming at least one conductive vertical stud on said surface; (B) blanket depositing a dielectric layer on said surface to imbed said pattern and said stud; (C) blanket coating a resist layer on said dielectric layer; (D) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric and resist layers, and continuing said etching to remove said resist layer concurrently with planarization of said dielectric layer; and (E) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric layer and said studs, and continuing second said etching to expose the top surface of each said stud in a substantially common plane with said dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification