Software protection system

• US 4,471,163 A
• Filed: 10/05/1981
• Issued: 09/11/1984
• Est. Priority Date: 10/05/1981
• Status: Expired due to Term

• Current Assignee: Chronoguard, L.L.C., Sarah Hollis Donald, The Chronoguard Trust, The Duty Trust, Thomas Christopher Donald
• Original Assignee: Henry W. Donald, Thomas C. Donald
• Inventors: Donald, Thomas C., Donald, Henry W.
• Primary Examiner(s): Cangialosi, Sal
• Application Number:
  US06/308,248
• Time in Patent Office: 1,072 Days
• Field of Search: 178/22.08, 178/22.19, 340/825.34, 364/200, 364/900
• US Class Current: 705/55
• CPC Class Codes: G06F 21/123 by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices

Abstract

A protection system for controlling the operation of a digital computer as to a particular program wherein a program "lock" interfaces with the computer and authorizes the operation in response only to a selected relation between a number in the program, a number in the lock, and a third number, a "key", supplied to the lock and which bears a selected relation to both the program number and lock number.

Claims

1. A system for limiting reproduction of an electrically representable process comprising:

process means for storing symbols U representative of a series of operations performable by a plurality of electrical signals U'"'"';

symbol generating and storage means for generating and storing a plurality of test symbols V representative of a go/no-go test and performable by a plurality of signals V'"'"';

storage means responsive to said process means and said symbol generating and storage means for storing a composite W of symbols U and V;

first translation and memory means for translating said symbols W, stored by said storage means into digitally encoded electrical signals W'"'"', including signals U'"'"' and V'"'"', representative of symbols U and V, respectively, and storing these signals;

key generating means comprising means responsive to symbols having, in part, a common derivative to that of said test symbols V for generating key symbols K;

second translation and memory means for translating symbols K, from said key generating means, into electrical signals K'"'"' and storing same;

signal processing means responsive to the receipt of said signals U'"'"' for the performance of said series of operations;

coupling means responsive to a selected input signal for coupling said signals U'"'"' from said first translation and memory means to said signal processing means; and

a process limiting means comprising;

correlation means including means for effecting a selected correlation between aspects of said signals V'"'"', from said first translation and memory means, and signals K'"'"', from said second translation and memory means, and for providing a correlation output signal which is a function of said correlation;

and

signal means responsive to a selected output of said correlation means for providing an input signal to said coupling means;

whereby, upon said selected output of said correlation means, the performance of said series of operations is enabled.

2. A system as set forth in claim 1 wherein:

said system includes lock identity code generating means for generating a selected class of electrical identification signals C'"'"' representative of identification symbols C;

said symbols to which said key generating means is responsive have a common derivative to that of said identification symbols C;

said process limiting means includes electronic locking means in turn including memory means responsive to said lock identity code generating means for storing said signals C'"'"';

said correlation means comprises a portion of said electronic locking means, and includes means further responsive to a selected correlation between signals C'"'"' and K'"'"' for providing said correlation output signal.

3. A system as set forth in claim 2 wherein:

said key generating means includes means for generating symbols A and B, representative of a selected real time period, and includable in said symbols K;

signals A'"'"' and B", representative of said symbols A and B and said selected real time period, are stored via said second translation and memory means;

said electronic locking means includes time generating means for generating signals T" indicative of current time; and

said correlation means comprises means responsive to a correlation between the said T" signal, output of said time generating means, and said A" and B" signals, aspects of said signals K'"'"', for enabling said correlation output signal of said correlation means.

4. A system as set forth in claim 3 wherein:

said symbol generating and storage means comprises means for generating said storing, as test symbols V, identity symbols S, algorithm symbols R directive of the generation of a random number X, represented by signals X'"'"', and algorithm symbols M directive of a selected combination of said symbols S and random number X;

said first translation and memory means comprises means having stored therein, as signals V'"'"', electrical signals S'"'"', R'"'"', and M'"'"', representative of symbols S, R, and M, respectively;

said key generating means is responsive to said symbols S, and signals S", representative of said signals S, are includable in said signals K'"'"' stored in said second translation and memory means;

said electronic locking means comprises;

discrete, independent signal generating means for generating signals M", representative of said symbols M, and

said means for effecting a selected correlation between aspects of said signals V'"'"' of said correlation means is responsive to said signals X'"'"' as an aspect of said signals R'"'"' from said first translation and memory means and signals S" as aspects of said signals K'"'"' from said second translation and memory means and said signals M" from said signal generating means for generating a first correlatable output signal F"; and

said signal means comprises;

signal combining means responsive to said signals X'"'"', S'"'"', and M'"'"' from said first translation and memory means for providing an intermediate signal output representative of a like response to that effected by said correlation means with respect to signals X'"'"', S", and M" for generating a second correlatable output signal F'"'"'; and

comparator means means responsive to a selected relationship between said correlatable output signals F'"'"' and F" for providing said input signal to said coupling means.

5. A system as set forth in claim 4 wherein:

said symbol generating and storage means includes means for generating and storing symbols N as elements of symbols V;

said system includes a digital computer, wjhich in turn includes said first and second translation and memory means, and said first translation and memory means having stored therein electrical signals S'"'"', R'"'"', N'"'"', and M'"'"', representative of the symbols S, R, N, and M, respectively;

said key generating means is responsive to said symbols N and S, and signals N" and S", representative of signals N and S, are included in said signals K'"'"' stored in said second translation and memory means; and

said correlation means comprising a portion of said electronic locking means is additionally responsive to a selected correlation of said signals N'"'"', as aspects of said signals V'"'"' from said first translation and memory means, and signals N" as aspects of said signals K'"'"' from said second translation and memory means for enabling the generation of said correlation output signal.

6. A system as set forth in claim 5 wherein:

said lock identity code generating means includes means responsive to discrete symbols P and Q for generating signals C'"'"';

said key generating means comprises means responsive to signals representative of said symbols P and Q for generating said symbols K and thereby signals K'"'"';

said key generating means is further responsive to signals representative of discrete symbols D for the generation of symbols K and thereby signals K'"'"';

said electronic locking means includes discrete, independent means for generating signals D'"'"' representative of symbols D; and

said correlation means comprising a portion of said electronic locking means is futher responsive to a selected correlation between said signals D'"'"' and said signals C'"'"' for providing said correlation output signal.

7. A system as set forth in claim 2 wherein:

said electronic locking means includes a container means for enclosing at least said memory means, and

electrical control means coupled to said container means and said memory means for altering said signal C'"'"' upon an entry into said container.

8. A system as set forth in claim 7 wherein said electrical control means includes bias means for supplying an operating bias to said memory means, and including means responsive to entry into said container means for interrupting said bias and thereby altering said signal C'"'"'.

9. A system as set forth in claim 4 wherein:

said correlation means comprises;

first conversion means for complementing bits of a first group of selected bytes of signals S", in instances where corresponding bits of signal X'"'"' are set, to provide a signal Y",

first multiplication means responsive to said signals S" and Y" for multiplying signal Y" by a second group of selected bytes of signal S" to provide a signal Z", and

first division means responsive to said signals S" and Z" for dividing signal Z" by a third group of selected bytes of signal S", and for providing as an output a signal representative of the remainder from the division, and being said first correlatable output signal F";

said signal means comprises;

second conversion means for complementing bits of a first group of selected bytes of signals S'"'"', in instances where corresponding bits of X'"'"', as per the selection of said first conversion means with respect to signals S", are set, to provide a signal Y'"'"',

second multiplication means responsive to said signals S'"'"' and Y'"'"' for multiplying signals Y'"'"' by a like second group of selected bytes of selected signals S'"'"' to the order of selection of said second group with respect to said signal S" by said first multiplication means to provide a signal Z'"'"', and

second division means responsive to said signals S'"'"' and Z'"'"' for dividing signals Z'"'"' by a like third group of selected bytes of signal S'"'"' to that provided said first division means with respect to signal S", and for providing a signal representative of the remainder of said last-named division, and being said second correlatable output signal F'"'"'.