Direct memory access logic system for a data transfer network

• US 4,471,427 A
• Filed: 12/01/1981
• Issued: 09/11/1984
• Est. Priority Date: 12/01/1981
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Corp (Unisys Corporation)
• Inventors: Harris, Craig W.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/326,335
• Time in Patent Office: 1,015 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A system provided within the Interface Circuit of a subsystem-controller for rapid and direct data transfer between the memory means of the subsystem controller and the main memory of a host computer or selected remote peripheral terminals.

Claims

1. In a peripheral-controller for a data transfer network wherein said peripheral-controller is made up of master and slave processor-controllers respectively having master and slave processor means and master and slave memory-controllers which use a commonly shared memory means, and wherein said peripheral-controller uses an interface circuit for communicating to a main host computer and also to a line communications processor connected to a plurality of remote peripheral terminals, a direct memory access logic system in said interface circuit for transferring data situated in said shared memory means to said line communications processor or for receiving data from said line communications processor for temporary storage in said shared memory means, said direct memory access logic system comprising:

(a) I/O bus from said master processor means for connecting said master processor means to a direct memory access logic unit, and for connecting said master processor means to said main host computer via said interface circuit which operates through a first distribution control circuit unit to said main host computer;

(b) said direct memory access logic unit being connected to said master processor means via said I/O bus, and functioning to receive direct memory access data transfer instructions from said master processor means, said direct memory access logic unit including;

(b1) a control register for holding direct memory access instructions received from said master processor means and for transmittal of said direct memory address instructions to a control logic means;

(b2) said control logic means, connected to receive said instructions from said control register, and having corrections for enabling direct output data transfers from said shared memory means via said master memory-controller, and connection to a direct memory access data driver means, said control logic means functioning to enable said direct memory access data driver means, and connected for enabling a bidirectional data bus means connected to said line communications processor to permit direct data transfer from said shared memory means to said line communications processor, said control logic means further connected to increment a direct memory access address counter and to decrement a direct memory access word transfer counter;

(b3) driver status means connected to said control logic means, said driver status means operating to sense the continuing existence of or the cessation of a direct memory access operating mode and connected to said I/O bus for signaling said master processor means;

(c) said direct memory access work transfer counter connected to said I/O bus, and loaded by said master processor, for counting the number of words transferred out of said shared memory means;

(d) said direct memory access address-counter, loaded initially by said master processor, for addressing said shared memory means via said master memory-controller, said address-counter being connected to said master memory-controller via said I/O bus for initiating addresses to said shared memory means;

(e) a direct memory access data driver connected to a memory data output bus of said master memory controller for receiving data transferred out of said shared memory means and transmitting said data to a bidirectional data bus;

(f) said memory data output bus connected from said master memory controller to said direct memory access data driver and functioning to directly transmit data from said shared memory means through said memory controller to said direct memory access data driver;

(g) said bidirectional data bus connected to said direct memory access data driver and to a line communications processor via a second distribution control unit and functioning, under control of said control logic means, to transfer data directly from said direct memory access data driver to said line communications processor;

(h) said master processor means including;

(h1) means for setting said direct memory access work transfer counter;

(h2) means for setting said direct memory access address counter;

(h3) means for requesting said first distribution control circuit unit to connect/disconnect said host computer to/from said interface circuit;

(h4) means for requesting said second distribution control circuit unit to connect/disconnect said line communications processor to/from said interface circuit;

(h5) means for initiating direct memory access instructions to said control register for setting up said direct memory access operating mode;

(i) said first distribution control circuit unit operating to connect/disconnect said main host computer to/from said interface circuit according to requests from either said main host computer or said master processor means;

(j) said second distribution control circuit unit operating to connect/disconnect said line communications processor to/from said interface circuit according to requests from said master processor means or said line communications processor;

(k) wherein said master processor means initiates a direct memory access mode transfer state by instructions to said control register of said direct memory access logic unit, to said direct memory access word counter, to said direct memory access address counter, and wherein said control logic means enables said direct memory access data driver and said bidirectional data bus to directly transfer data, via said master memory controller, from the said shared memory means to the said line communications processor.

2. In a peripheral-controller for a data transfer network wherein said peripheral-controller is made of master and slave processor-controllers each respectively having master and slave processor means and master and slave memory-controllers which use a commonly shared memory means, and wherein said peripheral-controller uses an interface circuit for communicating to a main host computer and to a line communications processor connected to a plurality of remote terminals, a direct memory access logic system in said interface circuit for transferring data to said shared memory means from said line communications processor, said direct memory access logic system comprising:

(a) an I/O bus for connecting said master processor means to a direct memory access logic unit, and also for connecting said master processor means to said main host computer via said interface circuit which operates through a first distribution control circuit unit to said main host computer;

(b) said direct memory access logic unit connected to said master processor means via said I/O bus, said logic unit for receiving direct memory access data transfer instructions from said master processor means, said direct memory access logic unit including;

(b1) a control register for holding direct memory access instructions from said master processor means and connected to transmit said direct memory access instructions to a control logic means;

(b2) said control logic means for enabling direct data transfers from said line communications processor to said shared memory means via said master memory-controller, said control logic means connected for enabling a bidirectional data bus to permit transfer from said line communications processor to a data receiver unit, said control logic means connected for enabling said receiver unit and to said I/O bus for data transfer to said shared memory means via said master memory controller, said controller logic means further connected to increment a direct memory access address-counter and to decrement a direct memory access word-transfer counter;

(b3) driver status means connected to said control logic means, said driver status means operating to sense the continuing existence of or the cessation of the direct memory access operating mode and connected to said I/O bus for signaling said master processor means;

(c) said direct memory access word-transfer counter connected to said I/O bus, and loaded by said master processor, for counting the number of words transferred into said shared memory means from said line communications processor;

(d) said direct memory access address-counter connected to said I/O bus, and loaded initially by said master processor, for addressing said shared memory means via said master memory controller to enable placement of data received from said line communications processor;

(e) said data receiver unit connected to receive input data from said line communications processor via said bidirectional data bus and to provide an output to said I/O bus for transmittal to said shared memory means via said master memory controller;

(f) said bidirectional data bus operating under the control of said control logic unit to transfer data from said line communications processor, via a second distribution control circuit unit, to said data receiver unit;

(g) wherein said master processor means further includes;

(g1) means for setting said direct memory access word transfer counter via said I/O bus;

(g2) means for setting said direct memory access address-counter via said I/O bus; and

(g3) means for requesting said first distribution control circuit unit to connect/disconnect said host computer to/from said interface circuit;

(g4) means for requesting said second distribution control circuit unit to connect/disconnect said line communication processor to/from said interface circuit;

(g5) means to initiate a direct memory access mode transfer state by transmitting instructions on said I/O bus to said control logic means via said control register, and to provide instruction data to said direct memory access word counter and to said direct memory access address-counter, via said I/O bus;

(h) wherein said control logic means enables said bidirectional data bus and said data receiver unit to directly move data from said line communication processor, via said second distribution control circuit unit, to said I/O bus for transfer of said data to said shared memory means via said master memory controller;

(i) said first distribution control circuit unit operating to connect/disconnect said main host computer to/from said interface circuit according to requests from either said main host computer or said master processor means;

(j) said second distribution control circuit unit operating to connect/disconnect said line communications processor to/from said interface circuit according to requests from said master processor means or from said line communications processor.