Microcomputer processor

• US 4,471,428 A
• Filed: 01/12/1982
• Issued: 09/11/1984
• Est. Priority Date: 01/12/1982
• Status: Expired due to Fees

• Current Assignee: Jury E. Chicherin, Pavel R. Mashevich, Sergei S. Kovalenko, Valery L. Dshkhunian, Vyacheslav V. Telenkov
• Original Assignee: Jury E. Chicherin, Pavel R. Mashevich, Sergei S. Kovalenko, Valery L. Dshkhunian, Vyacheslav V. Telenkov
• Inventors: Telenkov, Vyacheslav V., Kovalenko, Sergei S., Mashevich, Pavel R., Dshkhunian, Valery L., Chicherin, Jury E.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Watson, Mark P.
• Application Number:
  US06/338,886
• Time in Patent Office: 973 Days
• Field of Search: 364/200, 364/900
• US Class Current: 712/32
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers

Abstract

A microcomputer processor comprises a scratch-pad storage, an arithmetic-logical unit, an interface unit and a microprogram unit, all interconnected by means of an intraprocessor data bus, and a processor status register. The processor further comprises a constant file, first and second switching elements connected to the arithmetic-logical unit, a register, a source of logic potentials and a decoder. The present invention helps increase the speed of microcomputer processor and expand its functional capabilities.

Claims

1. A microcomputer processor designed for data processing, comprising:

a scratch-pad storage for storing digital data in the course of operation of said microcomputer processor;

a control input of said scratch-pad storage;

an arithmetic-logical unit for the conversion of said digital data;

an input, a control input and an output of said arithmetic-logical unit;

an interface unit for the exchange of said digital data;

a control input of said interface unit;

an intraprocessor data bus serving to interconnect said scratch-pad storage, said arithmetic-logical unit and said interface unit;

a microprogram unit for control over the execution of said digital data conversion and exchange in said microcomputer processor;

a first input of said microprogram unit connected to said intraprocessor data bus;

a second input of said microprogram unit;

an output of said microprogram unit connected to said control inputs of said scratch-pad storage, arithmetic-logical unit and interface unit;

a processor status register for storing the arithmetic operation code;

an input of said processor status register connected to said output of said arithmetic-logical unit;

an output of said processor status register connected to said second input of said microprogram unit; and

control input of said processor status register connected to said output of said microprogram unit;

a constant file;

an output of said constant file connected to said input of said arithmetic-logical unit;

a control input of said constant file;

a first switching element;

an output of said first switching element connected to said input of said arithmetic-logical unit;

a first input of said first switching element connected to said output of the processor status register;

a second input, a control input of said first switching element;

a second switching element;

an ouput of said second switching element connected to said input of said arithmetic-logical unit;

a first input, a second input a control input of said second switching element;

an instruction register for storing an instruction being executed;

an input of said instruction register connected to said intraprocessor data bus;

an output of said instruction register connected to said first input of said second switching element;

a source of logic potentials;

an output of said source of logic potentials connected to said second inputs of said first and second switching elements;

a decoder;

an input of said decoder, connected to said output of said microprogram unit;

an output of said decoder connected to said control inputs of said constant file and of said first and second switching elements.