Semiconductor memory
First Claim
1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
- a semiconductor substrate of a first conductivity type which has at least one well region of a second conductivity type;
an array of memory cells which are formed in said well region, each cell of said array including a MOS transistor of the first conductivity type and a capacitor;
a plurality of data lines which extend over said well region, and each of which is electrically connected to selected ones of said memory cells of said array;
a plurality of word lines which extend over said well region, and each of which is electrically connected to gates of the MOS transistors of selected ones of said memory cells of said array; and
a plurality of sense amplifiers each of which is coupled to a pair of adjacent ones of said data lines,said each sense amplifier including a pair of first MOS transistors of the first conductivity type which are formed in one well region of the second conductivity type formed in said semiconductor substrate, and a pair of second MOS transistors of the second conductivity type which are formed in said semiconductor substrate,wherein each transistor of said pair of first MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of first MOS transistors, wherein the drain of one of said transistors of said pair of first MOS transistors is electrically connected to one of said pair of data lines and the drain of the other of said transistors of said pair of first MOS transistors is coupled to the other of said pair of data lines,and further wherein each transistor of said pair of said second MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of second MOS transistors, wherein the drain of one transistor of said pair of second MOS transistors is electrically connected to one of said pair of data lines and the drain of the other of said transistors of said pair of said second MOS transistors is electrically connected to the other of said pair of data lines.
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Accused Products
Abstract
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
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Citations
19 Claims
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1. A semiconductor memory formed in a semiconductor integrated circuit comprising:
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a semiconductor substrate of a first conductivity type which has at least one well region of a second conductivity type; an array of memory cells which are formed in said well region, each cell of said array including a MOS transistor of the first conductivity type and a capacitor; a plurality of data lines which extend over said well region, and each of which is electrically connected to selected ones of said memory cells of said array; a plurality of word lines which extend over said well region, and each of which is electrically connected to gates of the MOS transistors of selected ones of said memory cells of said array; and a plurality of sense amplifiers each of which is coupled to a pair of adjacent ones of said data lines, said each sense amplifier including a pair of first MOS transistors of the first conductivity type which are formed in one well region of the second conductivity type formed in said semiconductor substrate, and a pair of second MOS transistors of the second conductivity type which are formed in said semiconductor substrate, wherein each transistor of said pair of first MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of first MOS transistors, wherein the drain of one of said transistors of said pair of first MOS transistors is electrically connected to one of said pair of data lines and the drain of the other of said transistors of said pair of first MOS transistors is coupled to the other of said pair of data lines, and further wherein each transistor of said pair of said second MOS transistors has its gate cross-coupled to the drain of the other transistor of said pair of second MOS transistors, wherein the drain of one transistor of said pair of second MOS transistors is electrically connected to one of said pair of data lines and the drain of the other of said transistors of said pair of said second MOS transistors is electrically connected to the other of said pair of data lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A dynamic type semiconductor memory comprising:
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a plurality of pairs of data lines to which memory cells are connected; differential amplifiers, each of which amplifies a difference between signal magnitudes appearing on each corresponding pair of data lines, said each differential amplifier including a pair of P-channel MOSFETs which have a drain and a gate of one cross-coupled to a gate and a drain of the other respectively and which have the drains connected to the corresponding pair of data lines respectively, a pair of N-channel MOSFETs which have a drain and a gate of one cross-coupled to a gate and a drain of the other and which have the drains connected to the corresponding pair of data lines respectively, and a circuit which controls positive feedback operations between the respective cross-coupled FETs of both FET pairs; a plurality of word lines, each of which is arranged in a manner to intersect with both of the pair of data lines; and a precharging circuit which sets said respective pairs of data lines at a potential intermediate between two potentials representative of binary signals to be stored in said memory cells prior to the start of positive feedback operations by said positive feedback operation control circuit. - View Dependent Claims (17, 18, 19)
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Specification