Multichannel programmable band comparator for apparatus used in cardiac surgery

• US 4,473,081 A
• Filed: 05/08/1981
• Issued: 09/25/1984
• Est. Priority Date: 05/14/1980
• Status: Expired due to Fees

• Current Assignee: Consiglio Nazionale Delle Ricerche (Repubblica Italiana)
• Original Assignee: Consiglio Nazionale Delle Ricerche (Repubblica Italiana)
• Inventors: Dioguardi, Nicola, Bertinetti, Mila, Allorio, Elena
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/261,778
• Time in Patent Office: 1,236 Days
• Field of Search: 128/670, 128/695, 128/696, 128/706, 128/709, 128/710
• US Class Current: 600/483
• CPC Class Codes: G16H 40/40 for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
• CPC Class Codes: G16H 40/63 for local operation

Abstract

A multichannel programmable band comparator is provided for apparatus used in cardiac surgery. A plurality of transducers supply signals relating to parameters such as the blood flow, arterial and venal pressure, body temperature and acid-base equilibrium to a multiplexer. The multiplexer supplies an analog-to-digital converter which is connected to a comparator. The comparator receives upper and lower limit values which are preset in a memory and operates a visual and acoustic alarm via a demultiplexer if any parameter is outside the band defined by the corresponding upper and lower limit values. The multichannel comparator may be used during open heart surgery, when the cardiocirculatory and respiratory functions of a patient are taken over by complex apparatus, to ensure that various physiological parameters remain within acceptable limits.

Claims

1. A multichannel programmable band comparators for use in cardiac surgery, comprising a plurality of transducers adapted to provide signals indicative of physical parameters of a patient, a multiplexer connected to said transducers to multiplex the signals thereof;

an analog-to-digital converter connected to said multiplexer to receive the multiplexed signals therefrom and to convert such signals into digital form;

an oscillator which generates an external clock timing signal which is conveyed to said analog-to-digital converter;

a memory block disposed to receive and store digital form information representing upper limit and lower limit values of said parameter;

a comparator block arranged to compare signals from said analog-to-digital converter with said upper limit and lower limit values obtained from said memory, a first counter that supplies the address of a parameter channel under examination to both said multiplexer and said memory to ensure correspondence between said analog-to-digital converter signals and upper limit and lower limit signals;

a control logic block connected to an output of said oscillator and to an output of said analog-to-digital converter, and alarm means connected to the output of said comparator block, said alarm means comprising a demultiplexer which receives said address from the first counter and from which alarm signals are supplied, and an alarm device connected to said demultiplexer to produce a visual and acoustic alarm when any of said signals from said analog-to-digital converter is outside said upper limit and lower limit values, and wherein said analog to digital converter supplies an end of conversion signal EOC, a control logic block connected to an output of said oscillator and to on output of said analog-to-digital converter in which said end of conversion signal EOC is processed together with a timing signal provided by said oscillator and which generates an enabling signal DEN for said demultiplexer to pass information on to said alarm device only when said end of conversion signal EOC has been received by said logic block.

2. An apparatus according to claim 1, wherein said memory block has adjusting means whereby said upper limit and lower limit values in said memory block are adjustable.

3. An apparatus according to claim 1, wherein said comparator block has means for comparing a variable number of body parameter signals.

4. An apparatus according to claim 1, further comprising an AUTO-MANUAL switch operable to selectively present said parameter signals for memory block comparison in a selected order;

and an internal timer for automatic operation when said switch is in the auto position.

5. An apparatus according to claim 1, further comprising means to indicate the number of the individual body parameters being analyzed in said comparator block.