System for providing short-term event data and long-term trend data

• US 4,475,558 A
• Filed: 07/09/1982
• Issued: 10/09/1984
• Est. Priority Date: 05/28/1982
• Status: Expired due to Fees

• Current Assignee: Healthdyne, Inc. (Abbott Laboratories), US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: Healthdyne, Inc. (Abbott Laboratories)
• Inventors: Brock, R. Wade
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/396,627
• Time in Patent Office: 823 Days
• Field of Search: 128/670, 128/695, 128/696, 128/702, 128/703, 128/704, 128/706, 128/708, 128/709, 128/710, 128/711, 128/716, 128/722, 128/723, 128/733, 128/902, 346/33 ME, 307/492, 33/1 C
• US Class Current: 600/523
• CPC Class Codes: A61B 5/0816 Measuring devices for examining respiratory frequency measuring frequency of electric signals G01R23/00
• CPC Class Codes: A61B 5/333 Recording apparatus specially adapted therefor
• CPC Class Codes: A61B 5/338 Recording by printing on paper
• CPC Class Codes: A61B 5/7232 involving compression of the physiological signal, e.g. to extend the signal recording period

Abstract

The system comprises first and second input circuits for receiving first and second parameter signals, respectively, from a patient monitor and producing first and second data signals. The first and second signals may be ECG and respiration signals, respectively. Each of the signals is passed directly to a switching circuit, and also passed through a time delay circuit which provides a time delay representation of the signal to the switching circuit. Also, the first signal is passed to a rate circuit which provides a rate signal indicative of the frequency of the first signal to the switching circuit. The switching circuit is operative to selectively connect the real time signals, time delayed signals or rate signal to an output circuit depending on the mode of operation of the system chosen. The output circuit can be connected to a strip chart recorder for providing a permanent readable record of the signal selected by the switching circuit.

Claims

1. For use with a patient monitor having a first parameter output for providing a first parameter signal associated with a patient being monitored and a second parameter output for providing a second parameter signal associated with said patient, a system for providing short-term event data and long-term trend data, comprising:

a first input circuit for receiving said first parameter signal and producing a first data signal;

frst time delay means for receiving said first data signal from said first input circuit, and delaying said first data signal by a first predetermined time to produce a delayed first data signal;

a second input circuit for receiving said second parameter signal and producing a second data signal;

second time delay means for receiving said second data signal from said second input circuit, and delaying said second data signal by a second predetermined time to produce a delayed second data signal;

a recorder having two recording channels, a high recording speed, and a low recording speed;

switch means for selectively connecting said second data signal, said delayed first data signal and said delayed second data signal to said recorder; and

mode control circuit means connected to said switch means for controlling the selective connection of signals to said recorder and controlling the recording speed of said recorder, said mode control circuit including at least one alarm input for receiving one alarm signal from said patient monitor, said mode control circuit means including means for producing a first mode of operation in which at least said second data signal is recorded on one of said recording channels at said low recording speed to provide said long term trend data, means for producing a second mode of operation in which said delayed first data signal and said delayed second data signal are recorded, respectively, on said two recording channels at a high speed, and mode change means for producing operation in said first mode in response to a first condition of said alarm input and for producing operation in said second mode for a predetermined period of time in resonse to a second condition of said alarm input,

wherein one of said first and second data signals is an ECG signal and the other of said first and second data signals is a respiration signal.

2. The system as set forth in claim 1 and further including rate circuit means connected to receive said first data signal and provide a rate signal indicative of the frequency of said first data signal, said first mode producing means controlling said switch means to connect said rate signal to said recorder during said first mode of operation.

3. The system as set forth in claim 2, said mode control circuitry including trend circuit means for producing a trend mode of operation by controlling said switch means to connect said second data signal and said rate signal to said output circuit regardless of the condition of said alarm input.

4. The system as set forth in claim 3 and further wherein said mode control circuit means includes event circuit means for producing an event mode of operation by controlling said recorder to be inoperative in the absence of an alarm signal on said alarm input and controlling said switch means to connect said delayed first data signal and said delayed second data signal to said first and second channels, respectively, and controlling said recorder to operate in said high speed in response to an alarm signal being received on said alarm input.

5. The system as set forth in claim 4 and further including a manually operated switch connected to selectively actuate either said mode change means, said trend circuit means, or said event circuit means.

6. The system as set forth in claim 2, wherein said first signal is an ECG signal having an R wave portion, and said rate circuit means comprises a filter for passing the R wave portion of said first signal, clock circuit means for producing clock signals at a predetermined rate, and counting means for counting the number of clock signals produced between a predetermined number of said R wave portions.

7. The system as set forth in claim 6, wherein said counting means includes a counting circuit connected to receive said clock signals and to count said clock signals and provide an output indicative of the count, a read only memory connected to receive the output of said counting circuit and produce a digital output indicative of a rate corresponding to the counting circuit output, and a gating circuit connected to receive the output of said read only memory, said gating circuit having an enable input and being responsive to a signal received on said enable input for passing said read only memory output, said counting circuit having a reset input connected to be actuated by one of said R waves, and said gating circuit enable input being connected to be actuated by said one of said R waves a predetermined time after actuation of said reset input.

8. The system as set forth in claim 7, wherein said gating circuit includes a digital-to-analog converter for converting said digital output from said read only memory to an analog signal representative of first rate.

9. The system as set forth in claim 8 and further including a filter connected to receive the analog signal from said digital-to-analog converter for smoothing said analog signal.

10. The system as set forth in claim 9 and further including an absence of signal circuit means for receiving signals passed by said threshold detection circuit means and producing an absence of R wave signal if no signal is passed by said detection circuit means within a predetermined time limit.

11. The system as set forth in claim 8, wherein said counting circuit comprises two serially connected counters, one of said counters being reset by each R wave and the other of said counters being reset a predetermined time after said one of said counters.

12. The system as set forth in claim 11, wherein said memory circuit is a random access memory.

13. The system as set forth in claim 12, wherein said random access circuit is dynamic, and further including refresh circuit means for refreshing said dynamic memory.

14. The system as set forth in claim 6 and further including threshold detection circuit means connected to receive signals passed by said R wave filter for passing only signals having a predetermined amplitude.

15. The system as set forth in claim 1, wherein said switch means also includes means for selectively connecting said first data signal to said recorder.

16. The system as set forth in claim 1 wherein said recorder is a strip chart recorder.

17. The system as set forth in claim 16 and further including circuit means for printing the time and date on an output of said strip chart recorder.

18. The system as set forth in claim 17, wherein said circuit means for printing time and date further includes means for providing an illuminated display of said time and date.

19. The system as set forth in claim 17, wherein said strip chart recorder includes circuitry for changing the speed of operation of said recorder, and said circuit means for printing time and date includes means for synchronizing the printing of time and date with the speed of said strip chart recorder.

20. The system as set forth in claim 17, wherein said circuit means for printing time and date includes an integrated circuit means for producing seven segment drive signals for time and date, converter means for converting said seven segment drive signals to binary coded decimal signals, and character generation means for receiving said binary coded decimal signals and producing dot matrix drive signals.

21. The system as set forth in claim 1, wherein said second input circuit includes a logarithmic compression circuit for logarithmically compressing said second signal thereby reducing the dynamic range of said second signal.

22. The system as set forth in claim 21 and further including a strip chart recorder for recording said logarithmically compressed second signal on paper, and further including a calibrated template for placing over said logarithmically compressed recoded second signal and providing a visual indication of linear increments of said second signal.

23. The system as set forth in claim 21, wherein said logarithmic compression circuit includes an operational amplifier and a plurality of diodes connected in a feedback circuit across said operational amplifier.

24. The system as set forth in claim 1, wherein said second time delay means comprises an analog-to-digital converter for converting said second data signal to digital signals, a memory circuit connected to receive said digital signals and having memory locations for storing digital signals representative of said second data signal for said second predetermined time, a digital-to-analog converter for receiving said digital signals from said memory circuit and converting said digital signals to an analog signal, and timing and control circuitry for periodically causing the information in each memory location to be read out to said digital-to-analog converter and new information to be written in from said analog-to-digital converter.

25. The system as set forth in claim 24, wherein said memory circuit comprises a random access memory.

26. The system as set forth in claim 25, wherein said random access memory comprises a static memory.

27. The system as set forth in claim 1, wherein said first input circuit includes a base line correction circuit comprising a voltage window circuit for producing a discharge signal when said first data signal is above or below predetermined upper and lower voltage limits, and discharge circuit means for momentarily causing capacitance voltages in said system to be discharged in response to said discharge signal.

28. The system as set forth in claim 27, wherein said input circuit includes a filter having an output line, and said discharge circuit means includes a transistor connected between said filter output line and ground.

29. The system as set forth in claim 28, wherein said transistor is a field effect transistor.

30. The system as set forth in claim 28, wherein said voltage window circuit comprises a pair of differential amplifiers, one of said differential amplifiers being connected to a positive reference source and the other of said differential amplifiers being connected to a negative reference source.

31. The system as set forth in claim 1, wherein said first input circuit includes an automatic gain control circuit for maintaining the amplitude of said first data signal within predetermined limits.

32. The system as set forth in claim 31, wherein said automatic gain control circuit includes a gain controllable amplifier connected to receive said first data signal, and a gain control circuit for sensing the output of said gain controllable amplifier and increasing or decreasing the gain of said gain controllable amplifier in response to said sensed output.

33. The system as set forth in claim 32, wherein said gain controllable amplifier includes an operational amplifier having a negative feedback path with a variable resistance optical coupler, said optical coupler having a control input connected to said gain control circuit.

34. The system as set forth in claim 32, wherein said gain control circuit includes an integrator circuit having an input connected to the output of said gain controllable amplifier and having an output connected to the control input of said optical coupler.

35. The system as set forth in claim 32 and further including a threshold circuit means for receiving said first data signal and passing only portions of said first data signal which have an amplitude which is greater than a predetermined value, and an absence of signal circuit for producing an absence of first signal output when no signal is passed by said threshold circuit means for a predetermined time duration, and fast restore circuit means for rapidly increasing the gain of said gain controllable amplifier in response to said absence of first signal output.

36. The system as set forth in claim 1, wherein said first time delay means comprises an analog-to-digital converter for converting said first data signal to digital signals and having sufficient memory locations for storing digital signals representative of said first data signal for said first predetermined time, a digital-to-analog converter for receiving said digital signals from said memory circuit and converting said digital signals to an analog signal, and timing and control circuitry for periodically causing the information in each memory location to be read out to said digital-to-analog converter and new information to be written in from said analog-to-digital converter.

37. The system as set forth in claim 1, wherein said switch means includes a manually operated switch for connecting said first data signal and said second data signal to said output circuit.

38. The system as set forth in claim 37 and further wherein said operated switch is connected to said strip chart recorder to cause said strip chart recorder to operate in a high speed.