Synchronous data bus with automatically variable data rate
First Claim
1. In a data processing system including processor means for processing said data, main memory means for storing said data, at least one peripheral device means, and bus system means for conducting information including main memory addresses and said data between said main memory means and said at least one peripheral device means, said bus system means comprising:
- bus means, includinga plurality of address/data lines for conducting said information,a clock line for conducting a clock signal, anda hold line for conducting a hold signal;
master controller means, includingclock means having an output connected to said clock line for providing a clock signal having a fixed clock signal period,master register means connected between said address/data lines and said main memory means and responsive to said clock signal for storing and transferring said information between said address/data lines and said main memory means in synchronization with said clock signal, andmaster hold control means having an output connected to and an input connected from said hold line, and(a) responsive to operation of said main memory means for providing said hold signal on said hold line during each said fixed clock signal period wherein said main memory means is not ready to receive said information provided on said address/data lines by said peripheral device means, and(b) responsive to said hold signal provided on said hold line during a said fixed clock signal period by a peripheral controller means associated with said peripheral device means for providing control signals to said master controller means and said main memory means to maintain said information stored in said master register means for transfer to said peripheral device means on said address/data lines during said fixed clock signal period; and
said peripheral controller means associated with each one of said peripheral device means, each one of said peripheral controller means includingperipheral register means connected between said address/data lines and said associated peripheral device means and responsive to said clock signal on said clock line for storing and transferring said information between said address/data lines and said associated peripheral device means in synchronization with said clock signal, andperipheral hold control means having an input connected from and an output connected to said hold line, and(a) responsive to operation of said associated peripheral device means for providing a hold signal on said hold line during each said clock signal period wherein said peripheral device means is not ready to receive said information provided on said address/data lines by said master controller means, and(b) responsive to said hold signal provided on said hold line by said master controller means during said fixed clock signal period for providing control signals to said associated peripheral device means and to said peripheral controller means to maintain said information stored in said peripheral register means for transfer to said master controller means on said address/data lines during said fixed clock signal period.
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Accused Products
Abstract
A digital data bus system operating asynchronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal. All information transfers are thereby synchronous with the single frequency bus clock, but data transfer rate is variable and automatically determined by the sending and receiving units.
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Citations
6 Claims
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1. In a data processing system including processor means for processing said data, main memory means for storing said data, at least one peripheral device means, and bus system means for conducting information including main memory addresses and said data between said main memory means and said at least one peripheral device means, said bus system means comprising:
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bus means, including a plurality of address/data lines for conducting said information, a clock line for conducting a clock signal, and a hold line for conducting a hold signal; master controller means, including clock means having an output connected to said clock line for providing a clock signal having a fixed clock signal period, master register means connected between said address/data lines and said main memory means and responsive to said clock signal for storing and transferring said information between said address/data lines and said main memory means in synchronization with said clock signal, and master hold control means having an output connected to and an input connected from said hold line, and (a) responsive to operation of said main memory means for providing said hold signal on said hold line during each said fixed clock signal period wherein said main memory means is not ready to receive said information provided on said address/data lines by said peripheral device means, and (b) responsive to said hold signal provided on said hold line during a said fixed clock signal period by a peripheral controller means associated with said peripheral device means for providing control signals to said master controller means and said main memory means to maintain said information stored in said master register means for transfer to said peripheral device means on said address/data lines during said fixed clock signal period; and said peripheral controller means associated with each one of said peripheral device means, each one of said peripheral controller means including peripheral register means connected between said address/data lines and said associated peripheral device means and responsive to said clock signal on said clock line for storing and transferring said information between said address/data lines and said associated peripheral device means in synchronization with said clock signal, and peripheral hold control means having an input connected from and an output connected to said hold line, and (a) responsive to operation of said associated peripheral device means for providing a hold signal on said hold line during each said clock signal period wherein said peripheral device means is not ready to receive said information provided on said address/data lines by said master controller means, and (b) responsive to said hold signal provided on said hold line by said master controller means during said fixed clock signal period for providing control signals to said associated peripheral device means and to said peripheral controller means to maintain said information stored in said peripheral register means for transfer to said master controller means on said address/data lines during said fixed clock signal period. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification