Insulated gate field effect transistor provided with a protective device for a gate insulating film

• US 4,481,521 A
• Filed: 08/24/1981
• Issued: 11/06/1984
• Est. Priority Date: 11/06/1978
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Okumura, Koichiro
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US06/295,367
• Time in Patent Office: 1,170 Days
• Field of Search: 357/23, 357/41, 357/51, 361/91, 361/56, 361/111
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An improved protective device for the gate insulation of an integrated-gate field effect transistor (IGFET) is disclosed that does not breakdown under spike-like input voltages. The protective device is formed on the same semiconductor chip as an operative IGFET and includes a resistor connected between the input terminal and the operative IGFET'"'"'s gate, a protective IGFET whose drain and gate are both connected to the operative IGFET'"'"'s gate, and another resistor connected between the protective IGFET'"'"'s source and a constant voltage source.

Claims

1. An insulated-gate field effect transistor device comprising:

an operative insulated-gate field effect transistor having a predetermined threshold voltage,

a protective insulated-gate field effect transistor having a threshold voltage substantially equal to said predetermined threshold voltage, whose drain and gate are coupled to the gate of said operative transistor,

a first resistive element coupled at one end to the gate of said operative transistor, the other thereof forming an input terminal and said first resistive element having a resistance value which is equal to or greater than the value of the dynamic resistance of the conducting source-drain path of the protective transistor and

a second resistive element connected at one end to the source of said protective transistor, the resistance value of said second resistive element being much smaller than said dynamic resistance and the other end of said second resistive element being coupled to a terminal for connection to a voltage source.

3. An insulated-gate field effect transistor device as claimed in claim 1, wherein the second resistive element has a resistance value of 50 to 100 ohms.

4. An insulated-gate field effect transistor device as claimed in claim 3, wherein the first resistive element has a resistance value of 500 ohms.

2. An insulated-gate field effect transistor device comprising:

an operative insulated-gate field effect transistor having a predetermined threshold voltage,

a protective insulated-gate field-effect transistor of having substantially the same threshold voltage as said predetermined threshold voltage, said protective insulated-gate field effect transistor having a drain and a gate coupled together to the gate of said operative transistor,

an input terminal,

a first resistive element coupled between said gate of said operative transistor and said input terminal,

a voltage terminal held at constant voltage having such a value that can make said operative transistor conductive if said constant voltage is applied to said gate of said operative transistor, and

a second resistive element connected between said voltage terminal and source of said protective transistor as the sole direct connection of a source-drain path of any transistor between said voltage terminal and said gate of operative transistor.

5. An insulated-gate field effect transistor device as claimed in claim 2, wherein the operative and protective transistors are formed on the same semiconductor integrated circuit chip and have gate insulating film thicknesses that are the same.

6. An insulated-gate field effect transistor device as claimed in claim 5, wherein the respective gate insulating film thicknesses are 300 to 1200 Angstroms.

7. An insulated-gate field effect transistor device comprising:

an operative field effect transistor having a source region and a drain region on a semiconductor substrate and a gate electrode disposed on said semiconductor substrate between said source and drain regions through a gate insulator film,

a protective field effect transistor having a source region and a drain region on a semiconductor substrate and a gate electrode disposed on said semiconductor substrate between said source and drain region through a gate insulator film having a thickness substantially equal to that of said insulator film of said operative field effect transistor, means for connecting said gate electrode and one of said drain and source regions of said protective field effect transistor to said gate electrode of said operative field effect transistor,

a first resistive element connected at one end to said gate electrode of said operative field effect transistor, the other end thereof being coupled to an input terminal, and

a second resistive element connected at one end to the other of said drain and source regions of said protective field effect transistor, the other end of said second resistive element being connected to a terminal held at a voltage sufficient to turn on said operative field effect transistor when said voltage is applied to said gate electrode of said operative field effect transistor, said second resistive element and the source-drain path of said protective field effect transistor being the sole direct connection via any source-drain path between said gate electrode of said operative field effect transistor and said terminal held at said voltage.

8. An insulated-gate field effect transistor device as claimed in claim 7, wherein said operative and protective field effect transistors are formed on a single semiconductor substrate.

9. An insulated-gate field effect transistor device as claimed in claim 8, wherein said second resistive element is formed on said semiconductor substrate as an extending region of said source region of said protective field effect transistor.

10. An insulated-gate field effect transistor device as claimed in claim 8, wherein said first resistive element is formed on said semiconductor substrate as an extending region of said drain region of said protective field effect transistor.