Direct memory access data transfer system for use with plural processors

• US 4,481,578 A
• Filed: 05/21/1982
• Issued: 11/06/1984
• Est. Priority Date: 05/21/1982
• Status: Expired due to Term

• Current Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Original Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Inventors: Hughes, Jodie K., Hagiwara, Sekine
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/380,962
• Time in Patent Office: 900 Days
• Field of Search: 364/200 MS File
• US Class Current: 709/212
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Apparatus for transferring data from the memory associated with one processor to the memory associated with another processor. A direct memory access (DMA) controller is connected to each processor and facilitates transfer of bulk data from one memory to the other without the intervention of either or both processors.

Claims

1. Apparatus for transferring data comprising:

(a) first processing means for handling data;

(b) first data storage means operatively connected to said first processing means for storing data;

(c) second processing means;

(d) second data storage means operatively connected to said second processing means for storing data; and

(e) data transfer means operatively connected to said first processing means, to said first data storage means and to said second data storage means for transferring data from said first data storage means to said second data storage means directly and without intervention of said porocessing means.

2. The apparatus in accordance with claim 1 wherein said data transfer means comprises a direct memory access controller.

3. The apparatus in accordance with claim 2 wherein said data transfer means further comprises an interprocessor communications bus operatively connected to said direct memory access controller.

4. The apparatus in accordance with claim 3 wherein said data transfer means further comprises an interprocessor communications controller operatively connected to said interprocessor communications bus for directing the transfer of data thereover.

5. The apparatus in accordance with claim 1 wherein said first processing means is a display processor and said second processing means is a mass memory data storage processor.

6. The apparatus in accordance with claim 5 wherein said display processor is a CRT processor.

7. The apparatus in accordance with claim 5 or 6 wherein said mass memory data storage processor is a disk processor.

8. The apparatus in accordance with claim 1 wherein said data storage means are random access memory devices.

9. The apparatus in accordance with claim 1 or 8 wherein said processing means are microprocessors.

10. Apparatus for transferring data from a first processor unit to a second processor unit, each of said processor units having a respective data storage means, comprising a direct memory access controller for transferring data from the first processor unit data storage means directly to the second processor unit data storage means.