Arrangement in a radar system for correction of phase and amplitude errors in a video signal

• US 4,484,194 A
• Filed: 08/31/1981
• Issued: 11/20/1984
• Est. Priority Date: 09/12/1980
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Arvidsson, Erik R.
• Primary Examiner(s): Wilbur, Maynard R.
• Assistant Examiner(s): Kaiser, K. R.
• Application Number:
  US06/297,836
• Time in Patent Office: 1,177 Days
• Field of Search: 343/5 NQ, 343/7.7, 343/7 A, 343/17.7, 324/58.5 R, 329/50, 331/4, 455/260
• US Class Current: 342/174
• CPC Class Codes: G01S 13/50 Systems of measurement based on relative movement of target
• CPC Class Codes: G01S 7/285 Receivers
• CPC Class Codes: H03D 1/2245 using two quadrature channels H03D1/2209 takes precedence

Abstract

An arrangement is provided for correcting the phase and amplitude errors occurring in the quadrature detector of a Doppler radar system. A correction unit (KE) is connected to both analogue-digital converters (AD1, AD2) in the I and Q channels to receive a radar signal which has been received by the system antenna and phase-detected in the quadrature detector (FD1, FD2, FS). The output of the correction unit (KE) is connected to a regulating network (RN) for sensing the output signals from the correction unit (KE) and controlling the latter so that the amplitude and phase errors (a'"'"' and θ'"'"') will be zero.

Claims

1. In the receiver of a coherent radar system, apparatus for generating from an input signal two signals in quadrature which are phase and amplitude corrected comprising:

first and second channels, said channels including quadrature detector means receiving the input signal and analog-digital converting means, having outputs, for converting the output of the quadrature detector means to digital values;

a correction means having first and second digital value inputs connected to the outputs of said analog digital converting means for receiving the quadrature digital values from said channels, first and second outputs for emitting phase and amplitude corrected quadrature digital values, and first and second modification inputs associated with the two quadrature digital values; and

a regulating means having first and second loops, said first loop including first multiplier means connected to the first and second outputs of said correction means for forming products of the emitted quadrature digital values, a first comparator means for emitting first binary values in accordance with the polarity of the products from said first multiplier means, and a first register means for storing said first binary values in order to form a first modification signal related to phase error, said first modification signal being fed to one of said modification inputs in response to the signal generated by said first comparator means, and said second loop including first difference forming means connected to the first and second outputs of said correction means for forming difference values of the emitted quadrature digital values, a second comparator means for emitting second binary values in accordance with the polarity of the difference values and second register means for storing said secondary binary values to form a second modification signal related to amplitude error, said second modification signal being fed to the other of said modification inputs, and said correction unit carrying out a correction of said quadrature digital value in one channel in dependence on said first and second modification signals whereby said quadrature digital values in said channels become orthogonal.

2. The apparatus of claim 1 wherein said correction means comprises second multiplier means connected to one of said digital value inputs and said one modification input for forming first product values, second difference forming means connected to said second multiplier means and the other of said digital value inputs for forming difference values, and third multiplier means connected to said second difference forming means and said other modification input for forming second product values, the output of said third multiplier means being connected to one of the outputs of said correction means.

3. The apparatus of claim 1 wherein said correction means comprises second multiplier means connected to one of said digital value inputs and said one modification input for forming first product values, third multiplier means connected to the other digital value input and said other modification input for forming second product values, and second difference forming means receiving said first and second product values for forming difference values, the output of said second difference forming means being connected to one of the outputs of said correction means.

4. The apparatus of claim 1 further comprising a summator means, the products formed by said first multiplier means for accumulating and said first comparator means compares the value of the accumulated products with a given constant value, the results of such comparison controlling the value of the first modification signal formed by said first register means.

5. The apparatus of claim 2 further comprising a summator means for accumulating the products formed by said first multiplier means, and said first comparator means compares the value of the accumulated products with a given constant value, the results of such comparison controlling the value of the first modification signal formed by said first register means.

6. The apparatus of claim 3 further comprising a summator means for accumulating the products formed by said first multiplier means, and said first comparator means compares the value of the accumulated products with a given constant value, the results of such comparison controlling the value of the first modification signal formed by said first register means.