Centralized hardware control of multisystem access to shared and non-shared subsystems

• US 4,484,270 A
• Filed: 07/07/1982
• Issued: 11/20/1984
• Est. Priority Date: 07/07/1982
• Status: Expired due to Term

• Current Assignee: Sperry Corporation
• Original Assignee: Sperry Corporation
• Inventors: Kriscunas, Joseph G., Quernemoen, John M., Campbell, Richard P., Voltz, Timothy R.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/395,936
• Time in Patent Office: 867 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/37
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register

Abstract

A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control one or more system'"'"'s accessibility to peripheral subsystem'"'"'s from a central location. It is able to provide this control with the capability of either allowing a peripheral subsystem to be concurrently accessed by more than one system or forcibly ensuring that the peripheral subsystem is exclusively accessible by only a single system.

Claims

1. A central controlling unit, for use with a plurality of data processing systems, none, some, or all of which are capable of being partitioned into a further plurality of separate entities, having the characteristics of a complete data processing system and a plurality of subsystem interface connections, said central controlling unit comprising:

enabling/disabling connection means connected to said plurality of subsystem interface connections for dynamically enabling/disabling, from a central location, said plurality of subsystem interface connections to selected entities and/or systems; and

means coupled to said enabling/disabling connection means for maintaining these enabled/disabled interconnections for as long as desired from undesired appropriation; and

storage means commonly connected to said enabling/disabling connection means and to said means for maintaining these interconnections, said storage means having residual information stored therein to cause various subsystem interconnections in response to corresponding system command signals.

2. A subsystem access unit which supports subsystem partitioning for multisystems and/or for multiprocessing systems comprising:

enabling/disabling connection means coupled to the interfaces of said subsystems for enabling/disabling said interfaces;

means coupled for receiving one or more command source signals associated with said multisystems and/or said multiprocessing systems to activate said enabling/disabling connection means; and

storage means commonly coupled to said enabling/disabling connection means and for receiving said command source signals, said storage means having stored therein resident information to cause various combinations of enabling/disabling interface connections and to enforce the integrity of said command source signals by preventing undesired misappropriation of said subsystems by preventing erroneous enabling/disabling of said subsystem interfaces.

3. A plurality of data processing systems, none, some or all of which are capable of being partitioned into a plurality of separate system entities, each data processing system and/or each entity comprising at least one central processor unit, at least one I/O processor, and at least one memory, at least one peripheral subsystem commonly connected to said plurality of data processing systems and/or said plurality of separate system entities, and a subsystem access unit commonly connected to said plurality of data processing system and/or separate system entities and to said at least one peripheral subsystem to enable/disable communication between the I/O processor of each of said pluralities of data processing systems and/or entities and said peripheral subsystem and to monitor and maintain accessibility/inaccessibility between the I/O processors and said peripheral subsystem.

4. The data processing system as set forth in claim 3 wherein said peripheral subsystem includes switching control means under the control of said subsystem access unit whereby portions of said switching means may be selectively activated/inactivated by said subsystem access unit to thereby provide selective communication between said I/O processors and said peripheral subsystem wherein said peripheral subsystem may be operated on a shared/nonshared basis by said I/O processors.

5. The invention as set forth in claim 4 wherein said system access unit comprises:

(a) a first interface means coupled to said plurality of data processing systems and adapted to receive commands from one or more command sources;

(b) a second interface means connected to the switching control means of the peripheral subsystem; and

(c) a microprocessing control system connected between said first and second interface means whereby certain commands received by the command interface provides selected switching control signals at said second interface to activate/deactivate selected switching portions of said switching control means thereby allowing communication between certain I/O processors and selected portions of said peripheral subsystem.

6. The invention as set forth in claim 5 wherein said microprocessing control system includes a plurality of microprocessors, a plurality of serial input/output means and a plurality of parallel input/output means.

7. The invention as set forth in claim 6 wherein said plurality of microprocessors includes a main and a redundant microprocessor which are operated constantly in phase while performing identical operations.

8. The invention as set forth in claim 7 wherein said microprocessing control system further includes a comparing means connected between said main and redundant microprocessors which constantly monitors the output signals of both microprocessors and indicates a miscompare signal whenever said main and redundant microprocessors provide different output signals.

9. The invention as set forth in claim 6 wherein said microprocessing control system includes a pair of serial input/output means associated with each of a plurality of channels.

34. The peripheral device as set forth in claim 9 wherein the pair of serial input/output means associated with each of a plurality of channels are interconnected in a manner to provide a redundant path for comparison by the microprocessor on incoming messages and to further provide a turnaround path for comparison by the microprocessor on outgoing messages and thereby accomplish an error checking function.

10. A subsystem access unit for use in conjunction with a, partitionable multisystem and/or a multiprocessing system, wherein each of said multiprocessing systems is capable of being partitioned into a plurality of separate entities, each entity having at least one instruction processor, at least one memory storage unit and at least one input/output processor, at least one peripheral subsystem, wherein said subsystem access unit is coupled to the data processing systems of said multisystem and/or to the entities of said multiprocessing system and includes means for enabling/disabling communication between input/output processors and said common peripheral subsystem, and enforcing exclusive use thereof once the communication link is enabled.

11. The invention as set forth in claim 10 wherein said centralized peripheral subsystem access means comprises:

(a) a plurality of command source interface means coupled to said data processing systems for receiving commands therefrom;

(b) a plurality of enabling/disabling means connected between said input/output means and said peripheral subsystem to providing selective intercommunication therebetween; and

(c) a control means coupled to said plurality of command source interfaces and connected to said plurality of enabling/disabling means for monitoring of the status of said enabling/disabling means by providing access to said enabling/disabling means when it is indicated, and for forcibly preventing such access when that is desired.

12. In a plurality of data processing systems, none, some or all of which are capable of being partitioned into one or more separate entities, said data processing system having more than one instruction processing means, more than one memory means, more than one input/output processing means and at least one peripheral subsystem, a centralized control system comprising:

(a) dynamically enabling/disabling means coupled between the peripheral subsystem means and the remainder of the means of the data processing systems to provide or prevent intercommunication therebetween;

(b) policing and enforcing means further coupled to said peripheral subsystem means to determine, monitor and maintain the accessibility or inaccessibility of said peripheral subsystem to one or more of said systems or partitionable portions; and

(c) central control means commonly connected to said data processing system and said peripheral subsystem to provide control for the dynamic enabling/disabling means and for the policing and enforcing means, via external, intelligent message protocols.

13. A centralized controlling system for use with a plurality of data processing systems each of the plurality of data processing systems capable of isolated performance, a peripheral subsystem coupled to said plurality of data processing systems for either shared or non-shared use by the separate ones of said data processing systems, said centralized controlling system comprising:

enabling/disabling means for dynamically enabling/disabling hardware communication links between the plurality of data processing systems and the peripheral subsystem;

further means coupled to said enabling/disabling means for policing and enforcing accessibility/inaccessibility of the peripheral subsystem once the enabling/disabling decision has been accomplished; and

controlling means commonly connected to said enabling/disabling means and said further means for providing this control via external, intelligent message protocols.

14. A subsystem access unit (SAU) for use in a partitionable multiprocessing system, said SAU comprising:

(a) means for the interface coupling of said SAU to one or more command sources;

(b) means for the interface coupling of said SAU to one or more shared peripheral interfaces;

(c) means for the interface coupling of said SAU to one or more serial channel transfer switch interfaces;

(d) means interconnected to (a), (b) and (c) for receiving information from said command sources, processing same, and therefrom providing switching information via said shared peripheral interfaces and said channel transfer switch interfaces which switching information is capable of not only enabling/disabling communication paths between a plurality of processing systems and a plurality of peripheral devices, but policing and enforcing said enabling/disabling decisions to allow exclusive use of a certain peripheral device by a certain system.

15. A method of dynamically disconnecting and/or exclusively connecting data processing systems and/or partitions/applications of partitionable multiprocessing systems to a peripheral subsystem through the use of the resident information of a subsystem access unit comprising the steps of:

(a) sending a first identifying request signal from a command source to said subsystem access unit;

(b) accessing a cabling information table within the resident information stored in said access unit;

(c) providing the identification of an input/output processor from said cabling information table;

(d) supplying the application number affected by this identified input/output processor from the input/output processor/application designation table within said stored resident information;

(e) supplying from a command source/application designation table of said resident information, the interface number assigned to that application;

(f) comparing the assigned command source interface number with the requesting command source interface number;

(g) if a mismatch exists, rejecting the request;

(h) if a match exists, determining if change can be made, using the partitioning status information status and the exclusive use status information;

(i) if change cannot be made, rejecting the request;

(j) if change can be made, effecting the change.

16. A method of dynamically changing the application assignments of peripheral units of a shared peripheral subsystem to other application assignments within a multiprocessor system and/or a multisystem by remotely controlling a switching peripheral control unit from a subsystem access unit comprising the steps of:

(a) sending a command request to said subsystem access unit requesting a particular interface;

(b) from a cabling information table within said subsystem access unit providing the identification number of the I/O processor making the request;

(c) using the input/output processor identification number, determine from the I/O processor/application designation table of the resident information which application is affected;

(d) using the application number, determine from the command source/application designation table of the resident information, the command source interface number assigned to that application number;

(e) compare this assigned command source interface number with the requesting interface number;

(f) if a mismatch exists, reject the request;

(g) if a match exists, determine if a change can be made using the resident information on partitioning and exclusive use status;

(h) if the change cannot be made, reject the request;

(i) if the change can be made affect the change.

17. A peripheral subsystem access unit for use in centrally controlling multisystem or multiprocessing system access to shared and non-shared peripheral subsystems comprising:

a microprocessing means;

a plurality of serial input/output circuits commonly coupled to said microprocessing means;

a plurality of parallel input/output circuits also commonly coupled to said microprocessing means;

a memory means coupled to said microprocessing means;

an input/output read selector connected to said plurality of serial and parallel input/output circuits;

a bidirectional data bus interconnected between said microprocessing means, said pluralities of serial and parallel input/output circuits, said memory means and said input/output read selector to provide a communication path therebetween;

a plurality of shared peripheral interface registers;

a plurality of byte channel transfer switch interface registers; and

another data bus interconnected between said pluralities of shared peripheral interface registers and said byte channel transfer switch interface registers and the plurality of parallel input/output circuits to provide a data path therebetween.

18. The peripheral subsystem access unit as set forth in claim 17 wherein the microprocessor includes means for generating a plurality of address signals and a plurality of control signals to supervise control of the signals along the bidirectional data bus.

19. The peripheral subsystem access unit as set forth in claim 18 wherein said plurality of address signals comprise a sixteen (16) bit address signal and said plurality of control signals comprise five (5) control signals.

20. The peripheral subsystem access unit as set forth in claim 19 wherein said five (5) control signals comprise an:

(a) Instruction fetch cycle signal;

a

(b) Memory operation signal;

an

(c) Input/output operation signal;

a

(d) Read signal and a

(e) Write signal.

21. The peripheral subsystem access unit as set forth in claim 20 wherein the microprocessor further includes means, using the address and control signals, for reading its program instructions from said memory and further means enabling it to perform the following operations under program control to:

(a) Read or write each serial input/output register;

to

(b) Read or write each parallel input/output register;

to

(c) Read or write into the memory; and

to

(d) Read data from the input/output read selector.

22. The peripheral subsystem access unit as set forth in claim 17 wherein each serial input/output circuit includes further means enabling it to translate a serial message from a 250K baud interface means into a series of eight bit bytes that can be read by the microprocessor or to translate bytes from the microprocessor into serial data for transmission on the 250K baud interface means.

23. The peripheral subsystem access unit as set forth in claim 17 wherein the interface read selector includes means for allowing the microprocessor to read a plurality of information bytes by doing an input/output operation.

24. The peripheral subsystem access unit as set forth in claim 17 wherein each of said parallel input/output circuits includes two eight (8) bit parallel input/output ports that can be used as input or output means, which ports are used to communicate with the shared peripheral interface registers and the byte channel transfer switching interface registers.

25. The peripheral subsystem access unit as set forth in claim 17 wherein the data bus interconnecting the shared peripheral interface registers, the byte channel switch interface registers and the plurality of parallel input/output circuits further includes:

(a) means for generating an interface address;

(b) means for generating write data for the interface registers;

(c) means for generating a write signal for the interface registers; and

(d) means to provide a read path for the data from the interface registers.

26. The peripheral subsystem access unit as set forth in claim 25 wherein the generated interface address comprises an eight bit signal capable of selecting an interface register for a read or write operation.

27. The peripheral subsystem access unit as set forth in claim 26 wherein the registers associated with the read path means capable of carrying the data from the interface are read only registers used as data assurance means whose bit status is maintained as an entry in a subsystem interface table in the memory means enabling the microprocessor to use these signals to read or write into the interface registers through the parallel input/output circuits.

28. The peripheral subsystem access unit as set forth in claim 27, wherein the contents of each of these interface registers are used to drive the shared peripheral interfaces and the byte channel transfer switch interfaces.

29. The peripheral subsystem access unit as set forth in claim 17 wherein said microprocessing means includes a further memory means.

30. The peripheral subsystem access unit as set forth in claim 17 wherein the memory means includes an error correction means.

31. The peripheral subsystem access unit as set forth in claim 30 wherein the memory error correction means is accomplished by means capable of error correction whenever reference is made to the information resident therein.

32. The peripheral subsystem access unit as set forth in claim 17 wherein further means are included for reading information from the byte channel transfer switch interface registers which indicates the enable/disable status of the interface channel.

33. The peripheral subsystem as set forth in claim 17 wherein further means are included for reading information from the shared peripheral interface registers which indicates the enable/disable status of that interface.