Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion

• US 4,484,272 A
• Filed: 07/14/1982
• Issued: 11/20/1984
• Est. Priority Date: 07/14/1982
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Green, Howard H.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US06/398,195
• Time in Patent Office: 860 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 717/149
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 9/35 Indirect addressing

Abstract

A digital computer executes a first instruction set in an interleaved fashion with second and third instruction sets, the latter two of which are executed at the same time. The first, second, and third instruction sets together represent an assignment statement of a high level programming language, such as ALGOL and COBOL, and by executing the first, second, and third instruction sets as recited above, a substantial improvement in the execution time of the corresponding assignment statement is attained. A second embodiment executes the first instruction set in an interleaved fashion with only the second instruction set to also achieve an improvement in execution time of the corresponding assignment statement.

Claims

1. A digital computer for executing a first instruction set in an interleaved fashion with second and third instruction sets both of which are executed at the same time, comprising:

means for fetching any instruction of said first set and for determining if the fetched instruction references two encoded addresses having the same predetermined code;

said encoded addresses having address bits which locate respective items in a memory, and having code bits which identify the nature of said items;

said predetermined code indicating the respective items are instructions in said second and third sets that compute addresses of two variables;

means for temporarily suspending operations on said fetched instruction of said first set if its referenced encoded addresses have said same predetermined code, and simultaneously executing said instructions of said second and third sets as located by said address bits in said encoded addresses to compute the addresses of said two variables; and

means for continuing operations on said fetched instruction of said first set after said instructions in said second and third sets have been simultaneously executed by performing a mathematical operation specified by said fetched instruction on said two variables.

2. A digital computer according to claim 1 which further includes a pair of independent bus means which serially couple together said means for fetching and determining, said means for temporarily suspending and simultaneously executing, and said means for continuing operations.

3. A digital computer according to claim 1 wherein said means for temporarily suspending operations on said fetched instruction and simultaneously executing said instructions of said second and third sets include a pair of means which respectively execute said instructions of said second and third sets in parallel.

4. A digital computer according to claim 1 and further including means for bypassing the execution of said instructions of said second and third sets and for inhibiting the suspending of operations on said fetched instruction of said first set if said code bits in said two encoded addresses have another code different from said predetermined code indicating the respective address bits directly locate said two variables in a memory.

5. A digital computer according to claim 1 wherein said means for temporarily suspending operations of said fetched instruction of said first set and simultaneously executing said instructions of said second and third sets includes a means for computing the addresses of respective indexed variables as the addresses of said two variables.

6. A digital computer according to claim 5 wherein said indexed variables are of the form A(I) where A( ) represents a list and A(I) represents the I-th item in said list at index I, A(I₁,I₂, . . . I_N) where A(, , . . . ) represents an N-dimensional matrix and A(I₁,I₂, . . . I_N) represents a particular item in said matrix at indices I₁ through I_N, and A(f(I)) where A(f( )) represents a set of indexed items and F(I) is an equation which identifies the I-th item in said set at index I.

7. A digital computer for executing first and second sets of instructions in an interleaved fashion, comprising:

means for fetching any instruction of said first set and determining if the fetched instruction references two encoded addresses respectively having first and second predetermined codes;

said encoded addresses having address bits which locate respective items in a memory, and having code bits which identify the nature of said items;

said first code indicating the item is a variable and said second code indicating the item is instructions in said second set that compute the address of another variable;

means for temporarily suspending operations on said fetched instruction if said encoded addresses have said first and second code and executing said instructions of said second set as located by said encoded address with said second code to compute said address of said another variable; and

means for continuing operations on said fetched instruction in said first set after said instructions of said second set have been executed by performing a mathematical operation specified by said fetched instruction on said variables.

8. A digital computer according to claim 7 which further includes a pair of independent bus means which serially couple together said means for fetching and determining, said means for temporarily suspending and instead executing, and said means for continuing operations.

9. A digital computer according to claim 7 wherein said means for temporarily suspending operations include a means for computing the address of an indexed variable as the address of said another variable.

10. A digital computer according to claim 9 wherein said indexed variable is of the form of A(I) where A( ) represents a list and A(I) represents the I-th item in said list at index I, A(I₁,I₂, . . . I_N) where A(, , . . . ) represents an N-dimensional matrix and A(I₁,I₂, . . . I_N) represents a particular item in said matrix at indices I₁ through I_N, and A(f(I)) where A(f( )) represents a set of indexed items and f(I) is an equation which identifies the I-th item in said set at index I.