Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion
First Claim
1. A digital computer for executing a first instruction set in an interleaved fashion with second and third instruction sets both of which are executed at the same time, comprising:
- means for fetching any instruction of said first set and for determining if the fetched instruction references two encoded addresses having the same predetermined code;
said encoded addresses having address bits which locate respective items in a memory, and having code bits which identify the nature of said items;
said predetermined code indicating the respective items are instructions in said second and third sets that compute addresses of two variables;
means for temporarily suspending operations on said fetched instruction of said first set if its referenced encoded addresses have said same predetermined code, and simultaneously executing said instructions of said second and third sets as located by said address bits in said encoded addresses to compute the addresses of said two variables; and
means for continuing operations on said fetched instruction of said first set after said instructions in said second and third sets have been simultaneously executed by performing a mathematical operation specified by said fetched instruction on said two variables.
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Accused Products
Abstract
A digital computer executes a first instruction set in an interleaved fashion with second and third instruction sets, the latter two of which are executed at the same time. The first, second, and third instruction sets together represent an assignment statement of a high level programming language, such as ALGOL and COBOL, and by executing the first, second, and third instruction sets as recited above, a substantial improvement in the execution time of the corresponding assignment statement is attained. A second embodiment executes the first instruction set in an interleaved fashion with only the second instruction set to also achieve an improvement in execution time of the corresponding assignment statement.
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Citations
10 Claims
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1. A digital computer for executing a first instruction set in an interleaved fashion with second and third instruction sets both of which are executed at the same time, comprising:
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means for fetching any instruction of said first set and for determining if the fetched instruction references two encoded addresses having the same predetermined code;
said encoded addresses having address bits which locate respective items in a memory, and having code bits which identify the nature of said items;
said predetermined code indicating the respective items are instructions in said second and third sets that compute addresses of two variables;means for temporarily suspending operations on said fetched instruction of said first set if its referenced encoded addresses have said same predetermined code, and simultaneously executing said instructions of said second and third sets as located by said address bits in said encoded addresses to compute the addresses of said two variables; and means for continuing operations on said fetched instruction of said first set after said instructions in said second and third sets have been simultaneously executed by performing a mathematical operation specified by said fetched instruction on said two variables. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A digital computer for executing first and second sets of instructions in an interleaved fashion, comprising:
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means for fetching any instruction of said first set and determining if the fetched instruction references two encoded addresses respectively having first and second predetermined codes;
said encoded addresses having address bits which locate respective items in a memory, and having code bits which identify the nature of said items;
said first code indicating the item is a variable and said second code indicating the item is instructions in said second set that compute the address of another variable;means for temporarily suspending operations on said fetched instruction if said encoded addresses have said first and second code and executing said instructions of said second set as located by said encoded address with said second code to compute said address of said another variable; and means for continuing operations on said fetched instruction in said first set after said instructions of said second set have been executed by performing a mathematical operation specified by said fetched instruction on said variables. - View Dependent Claims (8, 9, 10)
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Specification