Modular computer system
First Claim
1. A computer system comprisinga plurality of processing elements for simultaneously performing data processing calculations for a plurality of data processing tasks, each of said processing elements performing data processing calculations for one data processing task independently from other data processing elements;
- a common memory area having a plurality of storage locations, each of said plurality of storage locations being accessable by all of said processing elements; and
means responsive to request signals generated by said processing elements for temporarily selecting one of said processing elements generating a request signal, said temporarily selected processing element assigning portions of said common memory area to said data processing tasks.
6 Assignments
0 Petitions
Accused Products
Abstract
A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas.
The transfer of the supervisor function from processor to processor is performed by registering the supervisor'"'"'s identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.
Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.
-
Citations
33 Claims
-
1. A computer system comprising
a plurality of processing elements for simultaneously performing data processing calculations for a plurality of data processing tasks, each of said processing elements performing data processing calculations for one data processing task independently from other data processing elements; -
a common memory area having a plurality of storage locations, each of said plurality of storage locations being accessable by all of said processing elements; and means responsive to request signals generated by said processing elements for temporarily selecting one of said processing elements generating a request signal, said temporarily selected processing element assigning portions of said common memory area to said data processing tasks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer system comprising
a plurality of processing elements, each of said processing elements being assigned a unique identification number and being capable of performing data processing calculations simultaneously with and independently from other data processing elements; -
master interface means connected to all of said processing elements, said master interface means comprising, means for storing control information including the identification number of one of said processing elements, designated as the executive processing element; and means responsive to the storage of control information in said storage means for generating and forwarding interrupt signals, including said identification number, to all of said processing elements; and means located in said processing elements and responsive to said interrupt signals for initiating, in the processing element whose identification number is stored in said master interface, a predetermined routine for placing computing tasks in priority for subsequent execution by the processing elements. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. Arbitration circuitry for use in a computer system in which a plurality of devices are simultaneously attempting to gain access to a single resource, said arbitration circuitry comprising,
means for generating a plurality of fixed time intervals in a repetitive sequence with the total number of intervals being less than the total number of said devices; -
a plurality of access request leads, each of said leads being associated with one or more of said devices; means for assigning one or more of said time intervals in said sequence to each of said devices so that no two devices assigned to the same time interval are associated with the same access request leads; and means for generating an access request from a device attempting to access said resource on said access lead associated with said device during the time interval assigned to said device.
-
-
21. A computer system comprising
a plurality of processing elements, each of said processing elements being assigned a unique identification number and being capable of performing data processing calculations simultaneously with and independently from other data processing elements; -
a common processor bus connected to all of said processing elements; a common memory area having a plurality of storage locations, each of said plurality of storage locations being accessable by all of said processing elements; a system bus for forwarding information from said processing elements to said memory area; master interface means for forwarding information between said processor bus and said system bus, said master interface means comprising, a register for storing control information including the identification number of one of said processing elements, designated as the executive processing element; and interrupt control means responsive to the storage of control information in said storage means for generating and forwarding interrupt signals, including said identification number, to all of said processing elements; and means located in said processing elements and responsive to said interrupt signals for initiating, in the processing element whose identification number is stored in said master interface, a predetermined routine for placing computing tasks in priority for subsequent execution by the processing elements. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. Arbitration circuitry for use in a computer system in which a plurality of devices are simultaneously attempting to gain access to a single resource, said arbitration circuitry comprising,
a counter for generating a plurality of fixed time intervals in a repetitive sequence with the total number of intervals being less than the total number of said devices, said counter generating a synchronization signal one during each repetition of said sequence; -
a plurality of access request leads, each of said leads being associated with one or more of said devices; means for assigning one or more of said time intervals in said sequence to each of said devices so that no two devices assigned to the same time interval are associated with the same access request leads; means for generating an access request from a device attempting to access said resource on said access lead associated with said device during the time interval assigned to said device; a plurality of registers, one of said registers being associated with each of said time intervals; means responsive to said counter outputs for loading said access requests occurring during a time interval into the register associated with said time interval; and priority means responsive to said synchronization signal for selecting one of said registered access requests.
-
Specification