Serial data mode circuit for a memory

• US 4,484,308 A
• Filed: 09/23/1982
• Issued: 11/20/1984
• Est. Priority Date: 09/23/1982
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moench, Jerry D., Lewandowski, Alan J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Fleming, Michael R.
• Application Number:
  US06/422,047
• Time in Patent Office: 789 Days
• Field of Search: 365/189, 364/200, 364/900
• US Class Current: 711/109
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A serial data mode circuit, which provides valid data on a falling edge of a data valid signal, uses time between falling edges to prepare for the next falling edge in order to reduce the time between when a falling edge of the data valid signal occurs and when data actually becomes valid. A plurality of interconnected flip-flops selectively enable data latches containing data in response to a rising edge of the data valid signal. The data is then provided to a tri-state driver prior to the falling edge of the data valid signal. The tri-state driver is then enabled in response to the falling edge of the data valid signal.

Claims

1. In a memory for providing a plurality of data bits in response to a single address and providing the plurality of data bits in serial form in response to a data valid signal on an output terminal, a circuit comprising:

output means coupled to a common data bus for providing a data bit on the output terminal in response to each occurrence of the data valid signal;

a plurality of data latches coupled to the common data bus, each data latch containing data bit which is coupled to the data bus in response to receiving a data latch enable signal associated therewith; and

a plurality of interconnected flip-flops responsive to removal of the data valid signal for providing each of the data latch enable signals to the data latch with which it is associated in a predetermined sequence,

wherein a particular data latch is enabled by receiving the data latch enable signal with which it is associated sufficiently prior to the output means receiving the data valid signal so that the output means has received the data contained in the particular data latch on the common data bus prior to receiving the data valid signal.

2. A method for clocking data out of a memory system which has a plurality of data latches coupled to an output driver for selectively coupling data thereto in response to outputs provided by a plurality of registers coupled to the data latches, comprising:

clocking a first register on the rising edge of a first pulse of a column address signal so that the first register provides an output;

using the output from the first register to gate data out of a first data latch and through the output driver so that the output driver provides output data substantially on the falling edge of the first pulse;

inhibiting the first register and clocking a second register with a second pulse of the column address signal so that the second register provides an output;

using the output from the second register to gate data out of a second data latch and through the output driver so that the output driver provides output data substantially on the falling edge of the second pulse;

inhibiting the second register and clocking a third register with a third pulse of the column address signal so that the third register provides an output signal;

using the output from the third register to gate data out of a third data latch and through the output driver so that the output driver provides output data substantially on the falling edge of the third pulse; and

continuing inhibiting a previous register and clocking a succeeding register until all the registers have been clocked and then commencing with the first register again.

3. A circuit for providing serial data responsive to a data valid signal on an output terminal from a memory in response to a single address, comprising:

output means coupled to a common data bus for coupling a data bit received from said data bus to the output terminal in response to the data valid signal switching from a first level to a second level;

a plurality of data latches each coupled to the data bus, each data latch containing a data bit which is coupled to the data bus in response to receiving a data latch enable signal associated therewith; and

a plurality of interconnected flip-flops responsive to at least a portion of the address for providing a first data latch enable signal as determined by the address to the data latch associated with the first data latch enable signal prior to the data valid signal switching from a first level to a second level, providing a second data latch enable signal the data latch associated with the second data latch enable signal in response to the data valid signal switching from the second level to the first level, and removing the first data latch enable signal in response to providing the second data latch enable signal.

4. The circuit of claim 3 further comprising a buffer circuit interposed between the data bus and the output means.

5. The circuit of claim 4 wherein the plurality of data latches is further characterized as comprising first, second, third, and fourth data latches which couple a data bit to the data bus in response to first, second, third, and fourth data latch enable signals respectively;

and wherein the plurality of interconnected flip-flops is further characterized as comprising first, second, third, and fourth flip-flops, for sequentially providing the first, second, third, and fourth data latch enable signals.

6. The circuit of claim 5, wherein:

the first flip-flop has a first input for receiving the data valid signal, a second input, and an output for providing the first data latch enable signal;

the second flip-flop has a first input for receiving the data valid signal, a second input coupled to the output of the first flip-flop, and an output for providing the second data latch enable signal;

the third flip-flop has a first input for receiving the data valid signal, a second input coupled to the output of the second flip-flop, and an output for providing the third data latch enable signal; and

the fourth flip-flop has a first input for receiving the data valid signal, a second input coupled to the output of the third flip-flop, and an output coupled to the second input of the first flip-flop for providing the fourth data latch enable signal; and

wherein each flip-flop provides its respective data latch enable signal in response to the data valid signal switching from the second level to the first level when a data latch enable signal is present on its second input.