Neighborhood transformation logic circuitry for an image analyzer system

• US 4,484,346 A
• Filed: 04/28/1983
• Issued: 11/20/1984
• Est. Priority Date: 08/15/1980
• Status: Expired due to Term

• Current Assignee: David L. Mccubbrey, Ralph E. Richardson, Robert M. Lougheed, Stanley R. Sternberg, William O. Dargel
• Original Assignee: David L. Mccubbrey, Ralph E. Richardson, Robert M. Lougheed, Stanley R. Sternberg, William O. Dargel
• Inventors: Sternberg, Stanley R., McCubbrey, David L., Richardson, Ralph E., Lougheed, Robert M., Dargel, William O.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/489,669
• Time in Patent Office: 572 Days
• Field of Search: 382/41, 382/49, 382/27, 358/260, 358/261, 364/711, 364/715, 364/736, 364/768
• US Class Current: 382/303
• CPC Class Codes: G06T 7/00 Image analysis
• CPC Class Codes: G06V 10/42 Global feature extraction by analysis of the whole pattern, e.g. using frequency domain transformations or autocorrelation

Abstract

A system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image. The system includes a pipeline of substantially identical neighborhood transformation stages. Each stage includes a processor portion for analyzing the pixel values and a memory portion communicating with the processor portion for sequentially providing a window of neighboring pixels to the processor for analysis. A central programmable controller communicates with the pipeline over a single communication link which provides both the pixel value data to the pipeline and transformation control instructions to the processor portions of each stage. The memory portion preferably includes a random access memory which serves as a line storage device which may be readily adjusted to accommodate different raster scan line lengths from various image sensors. Each stage includes improved logic circuitry capable of performing a wide variety of analyses on both two-dimensional image data represented by binary pixel values and three-dimensional image data represented by multi-valued pixel values. Image border or off-image detection circuitry is also disclosed which is capable of detecting nonlinear boundaries for the image matrix.

Claims

1. In an image analyzer system having at least one substantially identical neighborhood transformation stage including a plurality of neighborhood window storage registers for temporarily accessing substantially all of the neighborhoods of pixel values in the image, and a programmable controller communicating with the stage wherein the improvement comprises a neighborhood transformation stage which can provide a wide variety of image analyses, said stage including:

logic means having at least two inputs and an output, operative to provide at its output the sum of two values applied to its inputs;

means for connecting said neighborhood window registers to one input of said logic means;

means coupled to the programmable controller for applying a programmable contribution value to the other input of said logic means;

detector means for detecting preselected output values from said logic means; and

maximum value detection means coupled to said logic means output for detecting the maximum value generated at said logic means output for the pixel values contained in said neighborhood window registers.

2. The improvement of claim 1 wherein said logic means is a digital adder device and wherein said stage further comprises:

multiplexer means having a plurality of inputs coupled to said neighborhood window registers, operative for sequentially coupling the pixel values contained in said registers to said one input of said adder means so as to provide pixel by pixel value analysis by said zero detector means and maximum value detection means coupled to the output of said adder means.

3. The improvement of claim 2 which further comprises:

means coupled to a multiplexer input associated with a particular neighborhood window register, operative to provide a correction value as a function of the pixel value contained in the center of said window; and

means coupled to the output of said multiplexer for modifying each of said pixel values with said correction value before they are applied to said one input of said adder means.

4. The improvement of claim 2 which further comprises:

shift register means coupled to the output of said zero detector means, said shift register means having a plurality of bit locations, wherein said zero detector means loads said shift register so that the state of each bit location is representative of the output of said zero detector means for each pixel value within the neighborhood window.

5. The improvement of claim 4 wherein said shift register means is a serial-in-parallel-out shift register in which the parallel output provides address information for accessing a memory, said address being a function of the output of said zero detector means for a particular neighborhood window.

6. The improvement of claim 3 wherein said maximum value detection means comprises:

comparison means having first and second inputs, and a first output for providing an output signal when the value presented at said first input is greater than the value presented at said second input; and

current maximum storage means having an input coupled to said comparison means first output for storing the current maximum pixel value as the pixels are sequentially presented to said adder means, said current maximum storage means having an output coupled to said second input of said comparison means so that said current maximum storage means provides a sequentially updated maximum value within the neighborhood window for comparison with subsequent pixel values.

7. The improvement of claim 6 which further comprises:

subtraction means for deleting the correction value from the maximum pixel value within a given neighborhood window.

8. The improvement of claim 6 which further comprises:

a second output for said comparison means for providing an output signal when the value presented at the first comparison means input is greater than or equal to the value presented at said second input;

a shift register having loading input means for loading the register, a clear input for clearing the contents of the shift register and an output;

flip flop means coupled between the loading input means of said shift register and the second output of said comparison means; and

means for coupling the first output of said comparison means to the clear input of said shift register whereby the state of the bit locations in said shift register pinpoints the location of pixels with the maximum value within the neighborhood windows.

9. The improvement of claim 8 which further comprises:

switching network means having inputs coupled to the output of said zero detector means, the first output of said comparison means, and the second output of said comparison means;

said switching network means having a first output line coupled to said flip flop means and a second output line coupled to said clear input of the shift register; and

means for selectively coupling the inputs of the switching network to its outputs depending upon the analysis to be carried out in that stage.

10. The improvement of claim 9 wherein said switching network couples the output of said zero detector means to the first output line of said switching network.

11. The improvement of claim 9 wherein said switching network couples the first output of said comparison means to said second output of the switching network and the second output of said comparison means to the first output of said switching network.

12. The improvement of claim 1 wherein said logic means is a binary adder device which includes a carry out output which generates a given value if the values at the inputs of said adder means causes same to generate a carry bit;

and

means for detecting the state of the carry out output of the adder means whereby pixel values within the window having a value greater than a given value may be detected.

13. The improvement of claim 12 which further comprises means for providing the two'"'"'s complement of the given value as the contribution value to the adder means.

14. The improvement of claim 2 which further comprises:

means coupled to one of said multiplexer inputs for detecting the value of the center pixel in the window;

summation means coupled to the output of said multiplexer for combining indicia of the center cell pixel value with each pixel value in the window; and

detector means coupled to the output of said summation means for detecting the state of the most significant bit of the combined value.

15. The improvement of claim 14 which further comprises:

shift register means having a plurality of bit locations corresponding to the pixel locations in the window; and

means for loading said bit locations in the shift register with the output of the most significant bit detector for each pixel value.