Circuit for amplitude and phase modulation of carrier signal by two respective input signals

• US 4,485,357 A
• Filed: 02/08/1982
• Issued: 11/27/1984
• Est. Priority Date: 03/09/1981
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Voorman, Johannes O.
• Primary Examiner(s): Grimm, Siegfried H.
• Assistant Examiner(s): Mis, David C.
• Application Number:
  US06/346,703
• Time in Patent Office: 1,023 Days
• Field of Search: 332/17, 332/21, 332/22, 332/23 R, 332/9 R, 332/40, 332/41, 332/48, 455/102
• US Class Current: 332/145
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 27/2082 for offset or staggered quadrature phase shift keying
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

An electronic arrangement for generating an amplitude and phase-modulated carrier signal having a phase modulation stage with two inputs for receiving two modulation signals, which modulation stage generates two different phase-modulated signals having the same carrier frequency and substantially the same amplitude, and an output stage to which the phase-modulated signals are applied for assembling by means of summation of the phase-modulated signals to produce the amplitude and phase-modulated carrier, the amplitude of which is modulated in dependence on the phase difference of the phase-modulated signals and the phase of which is modulated in dependence on the sum of the phases of the phase-modulated signals.

Claims

1. An electronic arrangement for generating an amplitude and phase-modulated carrier signal, said arrangement comprising a phase modulation stage having first and second inputs for receiving two respective modulation signals, said modulation stage being under the control of the modulation signals and generating in use two different phase-modulated signals having the same carrier frequency and substantially the same amplitude, and an output stage to which said phase-modulated signals are applied for assembling by means of summation of said phase-modulated signals to produce said amplitude and phase-modulated carrier signal the amplitude of which is modulated in dependence on the phase difference of said phase-modulated signals and the phase of which is modulated in dependence on the sum of the phases of said phase-modulated signals.

2. An electronic arrangement as claimed in claim 1, wherein said two modulation signals consist of a first modulation signal x₁ (t) and a second modulation signal x₂ (t) and said two phase-modulated signals are of the form Z₁ (t)=a cos (ω

_o t+ψ

(t)) and Z₂ (t)=a cos (ω

_o t+χ

(t)), the phase ψ

(t) of said first phase-modulated signal Z₁ (t) being equal to φ

(t)+θ

arccos (r(t)/2a)+m·

2π and

the phase χ

(t) of said second phase-modulated signal Z₂ (t) being equal to ##EQU12## wherein η

=±

1, it holding that η

=+1 when adding Z₁ (t)+Z₂ (t) to form the summation signal S(t) and η

=-1 when subtracting Z₂ (t) from Z₁ (t) to form the difference signal S'"'"'(t), and said modulation signals x₁ (t) and x₂ (t) representing the coordinates of a vector in a system of coordinates, which vector, when transformed into a system of polar coordinates, is represented by the quantities r(t) and φ

(t), wherein θ

=±

1, m, and n being integers and said amplitude and phase-modulated signal S(t) and S'"'"'(t) respectively being represented by r(t) cos (ω

_o t+φ

(t)).

3. An electronic arrangement as claimed in claim 2, wherein said phase modulation stage comprises a signal transforming arrangement and a phase modulation arrangement, said signal transforming arrangement is arranged for generating from said modulation signals x₁ (t) and x₂ (t) signals which are proportional to said phases ψ

(t) and χ

(t) and said phase modulation stage comprises phase modulators for generating said phase-modulated signals Z₁ (t) and Z₂ (t) from said signals which are proportional to the phases ψ

(t) and χ

(t).

4. An electronic arrangement as claimed in claim 3, wherein said signal transforming arrangement comprises an arccosine generator for generating the signal θ

arccos (r(t)/2a) from said modulation signals, and second and third summing arrangements to which the output signal of said arccosine generator and said signal φ

(t) are applied, for assembling in said second summing arrangement the phase signal ψ

(t)=φ

(t)+θ

arccos (r(t)/2a) by means of addition and for assembling the phase signal χ

(t)=φ

(t)-θ

arccos (r(t)/2a) in said third summing arrangement by means of subtraction.

5. An electronic arrangement as claimed in claim 1, wherein said phase modulation stage comprises a signal transforming arrangement and a phase modulation arrangement, said two modulation signals consist of a first modulation signal x₁ (t) and a second modulation signal x₂ (t), said signal transforming arrangement comprises a function generator connected to said inputs of said phase modulation stage for generating the signal E(t)=(1/r(t)) √

1-r² (t) from said modulation signals x₁ (t) and x₂ (t), two multiplying arrangements a first of which is connected to said first input and a second of which is connected to said second input and which are both connected to said function generator, a pulse signal generator connected to said two multiplying arrangements, said generator having a pulse repetition rate which is at least twice as high as the highest signal frequency of said modulation signals, said pulse signal representing a signal θ

, for forming in one multiplying arrangement the product signal θ

·

x₁ (t)·

E(t) and for forming in the other multiplying arrangement the product signal θ

·

x₂ (t)·

E(t), a fourth, fifth, sixth and seventh summing arrangement, the fourth summing arrangement being connected to said first input and to said second multiplying arrangement for forming the difference signal 1/2(x₁ (t)-θ

x₂ (t)·

E(t))=cos ψ

(t), the fifth summing arrangement being connected to said second input and said first multiplying arrangement for forming the sum signal 1/2(x₂ (t)+θ

x₁ (t)·

E(t))=sin ψ

(t), the sixth summing arrangement being connected to said first input and to said second multiplying arrangement for forming the sum signal 1/2(x₁ (t)+θ

x₂ (t)·

E(t))=cos χ

(t), and the seventh summing arrangement being connected to said second input and to said first multiplying arrangement for forming the difference signal 1/2(x₂ (t)-θ

x₁ (t)·

E(t))=sin χ

(t), and wherein the modulation arrangement comprises two quadrature modulators a first of which is connected to said fourth and fifth summing arrangements for forming the signal 1/2 cos (ω

_o t+ψ

(t))=Z₁ (t) and a second of which is connected to said sixth and seventh summing arrangements for forming the signal 1/2 cos (ω

_o t+ω

(t))= Z₂ (t).

6. An electronic arrangement as claimed in claim 3, wherein said signal transforming arrangement comprises a memory arrangement to which samples of said modulation signals x₁ (t) and x₂ (t) are applied as addressing signals and in each memory address there are stored output signals which are proportional to said phase signals ψ

(t) and χ

(t) and associated with each combination of signals x₁ (t) and x₂ (t) and wherein said memory arrangement comprises an addressing arrangement for reading out under the control of said addressing signals the output signals associated with each address.

7. An electronic arrangement as claimed in claim 2, wherein said phase modulation stage comprises a phase modulator connected to one of said inputs and having a carrier generator connected thereto for modulating the phase of a carrier signal with said modulation signal present on said input, a first comparator circuit having two signal input terminals a first input terminal of which is connected to said phase modulator and the second input terminal of which is connected to the other input for generating from said phase-modulated signal and said other modulation signal a first pulse-duration modulated signal with natural sampling, a second comparator circuit having a signal input terminal and a signal inverting input terminal, said signal inverting input terminal being connected to said phase modulator and said signal input terminal being connected to said other input for generating from said phase-modulated signal and said other modulation signal a second pulse-duration modulated signal with natural sampling, and a logic signal converter arrangement connected to the comparator circuits for generating said two phase-modulated signals Z₁ (t) and Z₂ (t) in hard-limited form from said pulse-duration modulated signals.

8. An electronic arrangement as claimed in claim 7, wherein said logic signal converting arrangement comprises first and second divide-by-two circuits connected respectively to said first and second comparator circuits, each divide-by-two circuit having two outputs for producing at a first output one of the two possible divided signals obtained by division by two of the pulse-duration modulated signals applied thereto and for producing at the second output the other divided signal obtained by means of division by two, a first exclusive-"OR"-gate circuit connected to said first output of said first divide-by-two circuit and to the first output of said second divide-by-two circuit, a second exclusive "OR"-gate circuit connected to said second output of said second divide-by-two circuit and to said second output of said first divide-by-two circuit, and wherein the outputs of the exclusive "OR"-gate circuits are outputs of said modulation stage.

9. An electronic arrangement as claimed in claim 7, wherein said comparator circuits each have a signal output and an inverting signal output and said logic signal converter arrangement comprises two flip-flop circuits each being only responsive to edges of one polarity, and wherein the inputs of one of said two flip-flop circuits are connected to said signal outputs of said two comparator circuits and the inputs of the other of said two flip-flop circuits are connected to said signal inverting outputs of said two comparator circuits, the outputs of said flip-flop circuits being the outputs of said modulation stage.

10. An electronic arrangement as claimed in any one of claims 1-9 wherein said output stage comprises an amplifying summing arrangement for amplifying and summing said phase-modulated signals Z₁ (t) and Z₂ (t) applied to said output stage and for assembling said signals to form said amplitude and phase-modulated output signal.

11. An electronic arrangement as claimed in claim 10, wherein said amplifying summing arrangement comprises two amplifiers for individually amplifying said phase-modulted signals Z₁ (t) and Z₂ (t), a hybrid circuit connected to the outputs of said amplifiers for assembling said phase-modulated signals supplied by the amplifiers to form said amplitude and phase-modulated signal and wherein the output of said hybrid circuit is the output of said output stage.

12. An electronic arrangement as claimed in claim 10, wherein said amplifying summing arrangement comprises a first logic "AND"-gate circuit, a second logic "AND"-gate circuit having two signal-inverting inputs, and a logic exclusive-NOR-gate circuit, one of ths signal inputs of said first "AND"-gate circuit, one of the inputs of said exclusive NOR-gate circuit and one of the inverting signal inputs of the said second "AND"-gate circuit being connected to one input of the output stage, the other signal input of said first "AND"-gate circuit, the other signal input of said exclusive NOR-gate circuit and the other signal-inverting input of said second "AND"-gate circuit being connected to the other input of the output stage, a three-state trigger circuit connected to said logic gate circuits and two current sources having control inputs which are connected to respective signal outputs of said three-stage trigger circuit, the outputs of said current sources being the output of the output stage.

13. An electronic arrangement as claimed in claim 10, wherein said amplifying summing arrangement comprises a transformer and two change-over switches having control inputs, the control inputs of said change-over switches are each connected to one respective input of the two inputs of said output stage, one of the contacts of each of the two change-over switches is connected to a first terminal of a voltage source, the other contact of each of the two change-over switches is connected to a second terminal of the voltage source with a voltage different from the first terminal, the switching arms of the change-over switches are interconnected via a primary winding of said transformer and wherein a secondary winding of said transformer is the output of the output stage.

14. An electronic arrangement as claimed in claim 10, wherein said amplifying summing arrangement comprises a transformer, a first current source and two change-over switches having control inputs, one of the contacts of each of the two change-over switches is connected to one end of the primary winding of said transformer, the other contact of each of the two change-over switches is connected to the other end of the primary winding of said transformer, the current source is connected between the switching arms of said change-over switches and wherein the control inputs of said change-over switches are each connected to a respective input of the two inputs of the output stage.

15. An electronic circuit as claimed in any one of claims 7-9, wherein said phase modulator comprises a phase-folding arrangement connected to an input for limiting the phase of the modulation signal present on said input terminal within the limits -π

/2 and +π

/2, said carrier generator having two outputs for supplying two carrier signals whose phases are shifted 90°

relative to each other, a further multiplier is connected to the phase-folding circuit and to one of the outputs of said carrier generator, a comparator circuit is connected to the multiplier and to the other output of said carrier generator and wherein a low-pass filter is connected to the output of the further comparator circuit.