Display control apparatus

• US 4,485,378 A
• Filed: 12/10/1981
• Issued: 11/27/1984
• Est. Priority Date: 12/11/1980
• Status: Expired due to Fees

• Current Assignee: Omron Tateisi Electronics Co. (Omron Corporation)
• Original Assignee: Omron Tateisi Electronics Co. (Omron Corporation)
• Inventors: Matsui, Kenji, Watanabe, Masakatu
• Primary Examiner(s): TRAFTON, DAVID
• Application Number:
  US06/329,506
• Time in Patent Office: 1,083 Days
• Field of Search: 340/750
• US Class Current: 345/28
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Abstract

A display comprises a relatively large plurality of picture elements in each of the vertical and horizontal directions, with which characters are displayed with a relatively less plurality of picture elements in each of the vertical and horizontal directions. In order to store the data to be displayed with the above described display, a refresh memory is employed. The refresh memory is used such that the respective areas thereof storing portions of the character are addressed in synchronism with the period of a character clock, whereby the character data to be displayed is read out therefrom. Each portion of the character data as read out from the refresh memory is latched in a latch circuit during the character clock period and is kept supplied to the display. The refresh memory serves to renew portions of the character at an arbitrary timing during the display period by the display or during the blanking period where display is not made by the display.

Claims

1. A display control apparatus for controlling operation of a display including a relatively large number of picture elements arranged both in vertical and horizontal directions and displaying a minimum unit of display data having a relatively small number of picture elements both in the vertical and horizontal directions, said display control apparatus comprising:

display data storage means for storing a plurality of said minimum units of display data to be displayed by said display,

means for generating read address data for designating addresses of data to be read from the data stored in said display data storage means,

means for generating write address data for designating addresses for writing in said display data storage means the display data of said minimum units of display data,

means for periodically generating a signal representing a minimum unit period, said minimum unit period being representative of a time required for one of said minimum units of display data to be displayed by said display,

means responsive to said minimum unit period representing signal for generating a latch enabling signal in a latch period within said minimum unit period and having a predetermined phase relative to said minimum unit period representing signal,

write data supply means for supplying said minimum units of display data,

writing means responsive to said write data for writing the same into said display data storage means as addressed by said write address data in a writing period contained within said minimum unit period but excluding the latch period such that said writing period and said latch period do not overlap, and

latch means responsive to said latch enabling signal for latching said minimum units of display data read from said display data storage means as addressed by said read address data and for supplying said display with said minimum units of display data.

2. A display control apparatus in accordance with claim 1, wherein

said writing means comprises

means for generating a write enabling signal in said writing period when said latch enabling signal is obtained from said latch enabling signal generating means, and

means responsive to said write enabling signal for selecting said write address data to apply the same to said display data storage means and responsive to the absence of said write enabling signal for selecting said read address data to apply the same to said display data storage means.

3. A display control apparatus in accordance with claim 1, wherein said display data storage means comprises refresh memory means.

4. A display control apparatus in accordance with claim 1, which further comprises buffer memory means for temporarily storing said write data supplied from said write data supply means for supplying said write data to said display data storage means.

5. A display control apparatus in accordance with claim 1, wherein

said display comprises a cathode ray tube display, and

said display data of each said minimum unit comprises data of one line of one character in the horizontal direction to be displayed with said cathode ray tube.

6. A display control apparatus in accordance with claim 5, which further comprises video signal generating means responsive to said display data stored in said latch means for generating a video signal for displaying said display data with said cathode ray tube display.

7. A display control apparatus in accordance with claim 1, wherein

said display data storage means includes a first storing region for storing fixed data and a second storing region for storing changeable data, and

said read address data generating means comprises

means for generating a fixed data read enabling signal having a predetermined period,

first address data generating means responsive to said fixed data read enabling signal for generating said address data of said first storing region, and

second address data generating means for generating read address data for reading said second storing region during a period in the absence of said fixed data read enabling signal.

8. A display control apparatus in accordance with claim 7, wherein

said write address data generating means comprises

third address data generating means for generating write address data,

fourth address data generating means for generating read address data of said first storing region,

said first address data generating means and said fourth address data generating means comprise common means.

9. A display apparatus comprising:

a display;

memory means for storing a plurality of minimum units of display data, each of said minimum units containing a small number of picture elements to be displayed by said display;

latch means connected between said memory means and said display for sequentially latching minimum units of display elements as they are read from said memory means for display by said display;

means for generating a clock signal having a period equivalent to the time required for the display of one of said minimum units;

read means for reading said minimum units from said memory means to said latch means;

write means for writing said minimum units into said memory means;

access control means for granting access of either said read means or said write means to said memory means;

access request means for generating an access request signal to said access control means, said access request signal having a first state for requesting access of one of said read means and said write means to said memory means and having a second state for requesting access of the other of said read means and said write means to said memory means, said access control circuit being responsive to said first state for immediately granting said one of read means and said write means access to said memory means, and being responsive to said second state for granting said other of said read means and said write means access to said memory means in a given clock period only if said second state occurs prior to said first state, otherwise, granting said other of said read means and said write means access to said memory means in the next succeeding clock period.

10. A display control apparatus as set forth in claim 9, including means for generating a latch enabling signal to said latch means for causing said latch means to latch said data read from said memory means, and wherein said generating means generates said latch enabling signal at a predetermined phase relative to said clock signal.