Global position system (GPS) multiplexed receiver

• US 4,485,383 A
• Filed: 12/01/1980
• Issued: 11/27/1984
• Est. Priority Date: 12/01/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Maher, Robert A.
• Primary Examiner(s): Tubbesing, T. H.
• Application Number:
  US06/211,500
• Time in Patent Office: 1,457 Days
• Field of Search: 343/100 ST, 370/104, 375/39, 375/114, 455/304, 455/305
• US Class Current: 342/352
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

A global position system (GPS) capable of multiple (two or more space vehicles) space vehicle (SV) multiplexing comprises an RF energy receiver for receiving high and low frequencies (L₁ and L₂) from a plurality of SVs on different codes, a switching means for alternately switching the RF receiver between the coded L₁, L₂ signals for detection, a digital processing means, replica coded L₁, L₂ signal producing hardware, and a coherent time and frequency synthesis means, said digital processing means connected to the RF receiver, coherent time and frequency synthesis means, and replica coded L₁, L₂ signal producing hardware for producing for the RF receiver replica coded L₁, L₂ signals for each SV to be tracked and adjusting with respect to the coherent time and frequency synthesis circuit the states of the hardware replica receiver signals to align them with corresponding signals of each of the SVs at a rate that supports sampled data closed-loop tracking of the SVs without reacquisition of each SV being tracked.

Claims

1. An RF receiver for a global positioning system capable of multiple space vehicle (SV) tracking comprising:

(a) an RF energy receiver for receiving coded high/low frequencies (L₁, L₂) from a plurality of SVs, each SV transmitting the L₁, L₂ signals on a code identifying the transmitting SV;

(b) a switching means for alternately switching the RF receiver between the coded L₁, L₂ signals for detetion and downconversion to baseband;

(c) a digital processing means,

(d) replica code and L₁, L₂ signal producing hardware; and

(e) a coherent time and frequency synthesis means connected to the RF receiver, replica code and L₁, L₂ signal producing hardware means and digital processing means, said digital processing means operatively connected to the RF receiver and replica coded and L₁, L₂ signal producing hardware means for producing RF receiver replica code L₁, L₂ signals for each SV to be tracked, and adjusting with respect to the coherent time and frequency synthesis circuit the states of the hardware replica receiver signals to align them with corresponding signals of each of the SVs at a rate that supports sampled data closed-loop tracking of the SVs without reacquisition of each SV being tracked.

2. An RF receiver for a global positioning system or the like including a sampled data closed-loop comprising:

(a) an RF receiver for selectively receiving high/low frequencies from a plurality of SV signals on different codes;

(b) a coherent time and frequency synthesis means operatively connected to the RF receiver;

(c) hardware circuit means connected to the RF receiver for providing replica receiver signals having a definite hardware tracking state; and

(d) a digital processing means, said digital processing means including a carrier and code frequency word generating means operatively connected to the RF receiver and hardware circuit means for adjusting with respect to the coherent time and frequency synthesis circuit the states of the hardware replica receiver signals of the hardware circuit means such that the hardware replica signals are in alignment with each of the corresponding signals of the plurality of SVs being tracked for maintaining information of the hardware tracking state for each of said plurality of SV signals and for sequentially setting up the replica hardware for the next cycle of operation on a given code and frequency and providing the receiver measurement outputs whereby the digital processing means controls the hardware circuit means in complete detail and keeps track of the state of the hardware circuit means in complete detail thereby achieving multiplexed operation in which the hardware circuit means is assigned sequentially to a plurality of SV signals at a switching rate that supports sampled data closed-loop tracking of the code and carrier signal components of each SV without the need for repetitive reacquisition of the signals.

3. An RF receiver for a global positioning system according to claim 2 wherein said hardware circuit means connected to the RF receiver and coherent time and frequency synthesis circuit for producing replica receiver signals having a definite hardware tracking state comprises:

a local carrier replicate generation hardware circuit means connected to the digital processing means and coherent time and frequency synthesis circuit for receiving from the digital processing means carrier phase information and a Doppler frequency data word, and from the coherent time and frequency synthesis circuit a selected reference frequency for producing an LO signal of the Doppler frequency word and reference frequency for the RF receiver.

4. An RF receiver according to claim 3 wherein the local carrier replicate generation hardware circuit means comprises:

(a) a carrier digital oscillator, said carrier digital oscillator including a phase holding register (latch) connected to the carrier master accumulator of the baseband processor for receiving the carrier phase information to preset the phase, a frequency holding register connected to the summer of the baseband processor for holding the Doppler frequency data word, a phase accumulator means, a frequency holding register, the phase accumulator means connected to the frequency holding register (latch) for accumulation as the carrier frequency word;

(b) read only memory/digital to analog converters (ROM/DACs) for conversion of the phase accumulator means output to digital sine and cosine signals to analog amplitudes; and

(c) a signal sideband mixer connected to the ROM/DACs and coherent time and frequency synthesis circuit for combining the carrier difference Doppler frequency with a reference frequency for the RF receiver.

5. An RF receiver according to claim 2 wherein said hardware circuit means connected to the RF receiver and coherent time and frequency synthesis circuit for producing replica receiver signals having a definite hardware tracking state comprises:

a local code replicate generation hardware circuit means connected to the digital processing means and coherent time and frequency synthesis circuit for receiving from the digital processing means code runup control signals and code frequency words and from the coherent time and frequency synthesis circuit a selected reference for producing phase representing signals for producing pseudo noise, code α and

code β

signals for the RF receiver.

6. An RF receiver according to claim 5 wherein the local code replicate generation hardware circuit means comprises:

(a) a digital oscillator having a code runup control register connected to the code master accumulator of the digital processing means, a code frequency holding register connected to the summer of the digital processing means for receiving the code frequency word, a holding register connected to the code runup control register and code frequency word holding register for selectively receiving the code frequency word and code runup word, a phase accumulator means connected to the holding register for selectively setting the phase accumulator means to zero phase (feathering), for running up the integer code state to the real code state required, and for producing a code Doppler frequency for a forthcoming sample interval whereby the feathering, set, runup, and steady-state frequency synthesis execution across the multiplex interrupt boundry is controlled;

(b) ROM/DCAS connected to the phase accumulator means for converting the phase outputs of the phase accumulator means to analog amplitudes;

(c) resolver connected to the ROM/DACS and coherent time and frequency synthesis circuit for mixing their outputs with a selected reference frequency;

(d) a code setter means connected to the resolver, a p-(precision) code generator and a ca-(coarse acquisition) code generator connected to the code setter means, said code setter means operative to synchronize the p-code generator and ca-code generator in response to the digital processing means space vehicle (SV) code selection to set the SV code identification in the p-code and ca-code generators; and

(e) an output selector connected to the p-code and ca-code generators for selectively outputting SV pseudo noise signals, designated code α and

code β

signals to the RF receiver for multiplexing space vehicle identifying codes to the RF receiver for SV multiplexing.