Integrated circuit dual polarity high voltage multiplier for extended operating temperature range

• US 4,485,433 A
• Filed: 12/22/1982
• Issued: 11/27/1984
• Est. Priority Date: 12/22/1982
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation
• Inventors: Topich, James A.
• Primary Examiner(s): Shoop, William M.
• Assistant Examiner(s): Ault, Anita M.
• Application Number:
  US06/452,239
• Time in Patent Office: 706 Days
• Field of Search: 363/59, 363/60, 363/61, 363/65, 307/110
• US Class Current: 363/60
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

Disclosed is an on-chip, dual polarity high voltage multiplier circuit consisting of a main high positive voltage multiplier and high negative voltage multiplier and an auxiliary high negative voltage multiplier coupled to the main multipliers to prevent turning on of parasitic transistors associated with the MOS diodes of the main multipliers and thereby extend the operating temperature range to 150° C. and improve the fall time of the dual polarity multiplier. The auxiliary multiplier may be located in a common p-well with the main positive and negative multipliers or with the main negative multiplier and its output voltage is connected to this common well.

Claims

1. A dual polarity voltage amplifier integrated circuit on a semiconductor substrate of a first conductivity type having an isolated region of an opposite conductivity type, said circuit comprising:

a positive voltage multiplier consisting of a plurality of coupling capacitors and metal-oxide-semiconductor (MOS) diodes connected together for generating a positive output voltage, said MOS diodes being located in said isolated region;

a negative voltage multiplier consisting of a plurality of coupling capacitors and MOS diodes for generating a negative output voltage, said negative multiplier MOS diodes being located in said isolated region; and

an auxiliary voltage multiplier consisting of a plurality of coupling capacitors and MOS diodes for generating a negative output voltage more negative than said negative multiplier output, said auxiliary multiplier MOS diodes being located in said isolated region and said auxiliary multiplier output applied to said isolated region.

2. A dual polarity voltage multiplier integrated circuit on a semiconductor substrate of a first conductivity type having a plurality of isolated regions of a conductivity type opposite to said first conductivity type, said circuit comprising:

a positive voltage multiplier having a plurality of coupling capacitors and metal-oxide-semiconductor (MOS) diodes connected together for generating a positive output voltage, said MOS diodes being located in a first isolated region;

a negative voltage multiplier having a plurality of coupling capacitors and MOS diodes connected together for generating a negative output voltage, said negative multiplier MOS diodes being located in a second isolated region; and

an auxiliary negative voltage multiplier having a plurality of coupling capacitors and MOS diodes connected together for generating a negative output voltage more negative than the output voltage of said negative multiplier, said auxiliary multiplier MOS diodes being located in a third isolated region and said auxiliary multiplier output voltage applied to said second and third isolated regions.

3. The circuit as in claim 2 wherein the coupling capacitors are parallel polysilicon plate capacitors.

4. The circuit as in claim 2 wherein the coupling capacitors constituting said positive voltage multiplier and negative voltage multiplier are parallel polysilicon plate capacitors and the coupling capacitors constituting the auxiliary multiplier are depletion-mode devices.

5. The circuit as in claim 2 wherein said substrate is n-type single crystal silicon and said first and second regions are p-type epitaxial silicon.

6. A voltage multiplier circuit on an n-type semiconductor substrate having a first and second p-type isolated regions thereon, said circuit comprising:

a first voltage multiplier having a plurality of coupling capacitors and metal-oxide-semiconductor (MOS) diodes connected together for generating a negative voltage output, said first multiplier MOS diodes being located in said first p-type region; and

a second voltage multiplier having a plurality of coupling capacitors and MOS diodes connected together for generating a negative voltage output more negative than said first multiplier output, said second multiplier MOS diodes being located in said second p-type region and said second multiplier output connected to said first and second p-type regions.

7. The circuit as in claim 6 further comprising a third voltage multiplier having a plurality of coupling capacitors and MOS diodes connected together for generating a positive voltage output, said third multiplier MOS devices being located in said first or second p-type region.

8. The circuit as in claim 7 wherein said substrate is single crystal silicon and said p-type regions are epitaxial silicon.

9. A dual polarity high voltage multiplier integrated circuit on an n-type semiconductor silicon substrate having an isolated p-type expitaxial silicon region thereon, said circuit comprising:

a first voltage multiplier having a plurality of coupling capacitors and n-channel MOS diodes connected together for generating a high positive voltage output, said MOS diodes being located on said epitaxial region;

a second voltage multiplier having a plurality of coupling capacitors and n-channel MOS diodes connected together for generating a low negative voltage output, said second multiplier MOS diodes being located in said epitaxial region; and

a third voltage multiplier having a plurality of coupling capacitors and n-channel MOS diodes connected together for generating a negative voltage output which is more negative than said second multiplier voltage output, said third multiplier MOS diodes being located in said epitaxial region and said third multiplier output applied to said epitaxial region.

10. The circuit as in claim 9 wherein said coupling capacitors are parallel polysilicon plate capacitors located on said substrate.