Standard hardware-software interface for connecting any instrument which provides a digital output stream with any digital host computer

• US 4,485,439 A
• Filed: 07/27/1982
• Issued: 11/27/1984
• Est. Priority Date: 07/27/1982
• Status: Expired due to Fees

• Current Assignee: S.A. Analis
• Original Assignee: S.A. Analis
• Inventors: Rothstein, Robert
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/402,385
• Time in Patent Office: 854 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/63
• CPC Class Codes: G16H 40/63 for local operation
• CPC Class Codes: G16H 40/67 for remote operation
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass

Abstract

A microprocessor-controlled interface for permitting any digital host computer to receive serial digital data from any instrument wherein (a) the time at which digital data from the instrument is to enter the host computer and (b) the logical structure of the digital data entering the host computer are controlled by instructions from the host computer to the microprocessor and wherein (a) physical formatting incompatabilities between the host computer and the instrument and (b) the communicating of prohibited characters from the instrument to the host computer and vice versa are avoided. The timing control and logical structure of the digital data are effected by directing data from the instrument into a scratchpad memory, which is divided into records pursuant to instructions from the host computer, the contents of the scratchpad memory being sent to the host computer upon a corresponding instruction therefrom. A terminal for communicating with the host computer and the instrument may be included. Physical formatting discrepancies are avoided by translating inputs to the interface into a common physical format and translating outputs from the interface into the physical format of the instrument, host computer, or terminal which is receiving such outputs.

Claims

1. In a communication system having a digital host computer and an instrument which generates a stream of serial digital outputs, a universal communication interface coupled between the host computer and the instrument, the interface comprising:

a microprocessor having executive means for executing instructions entered by the host computer into the microprocessor, the instructions forming a set of distinct instructions; and

a scratchpad memory for receiving and storing digital signals;

wherein the executive means divides the scratchpad memory into a defined structure of at least one record in response to the receiving of at least one corresponding instruction having a selectable variable portion from the host computer, the selected variable portion determining the defined structure of the scratchpad memory and wherein digital signals, corresponding to the digital outputs from the instrument, are directed into and in conformance with the defined structure of one of the at least one record in response to a corresponding instruction from the host computer.

2. An interface according to claim 1 wherein the instrument is coupled to the scratchpad memory by a first channel and wherein the first channel is selectively closed by the executive means in response to a corresponding instruction entered by the host computer.

3. An interface according to claim 2 wherein the host computer communicates digital data in a first physical format and the instrument communicates digital data in a second physical format, the interface further comprising:

physical compatibility means for (a) conforming all digital signals entering the interface from the computer and the instrument into a standard physical format compatible with the microprocessor means and (b) conforming the digital signals exiting the interface into the first physical format or the second physical format depending on whether the host computer or the instrument, respectively, is the destination of the exiting signals.

4. An interface according to claim 3 wherein the first physical format differs from the standard physical format and the second physical format differs from the standard physical format, and wherein the physical compatibility means comprises:

a first translator element connected between the executive means and the instrument, the first translator element changing the physical format of digital signals communicated to and from the instrument to effect physical compatibility, and

a second translator element connected between the executive means and the host computer, the second translator element changing the physical format of digital signals communicated to and from the host computer to effect physical compatibility.

5. An interface according to claim 1 further comprising:

means for converting prohibited digital data characters from the instrument into digital characters which are allowed inputs to the host computer.

6. An interface according to claim 4 further comprising:

means for converting prohibited digital data characters from the instrument into digital characters which are allowed inputs to the host computer.

7. An interface according to claim 5 wherein the converting means changes any digital character which corresponds to a control character in the host computer into a digital character which does not correspond to a host computer control character.

8. An interface according to claim 3 wherein the common physical format is asynchronous ASCII and wherein distinct instructions includes a multi-character mnemonic which includes a two character prefix, wherein the two-character prefix is @@ which represents 64₁₀ 64₁₀ in ASCII.

9. An interface according to claim 4 wherein the second translator element is incorporated with the executive means into a single unit.

10. An interface according to claim 6 further comprising:

means for selectively deleting portions of digital output from the intstrument.

11. An interface according to claim 10 wherein the converting means and the deleting means comprise programmable ready-only memory (PROM) which is adapted to each distinct instrument coupled to the interface.

12. An interface according to claim 1 wherein the scratchpad memory temporarily stores the digital signals corresponding to the digital outputs from the instrument, the digital signals in the stratchpad memory being directed toward the host computer in response to a corresponding instruction by the host computer to the microprocessor means.

13. An interface according to claim 10 wherein the scratchpad memory temporarily stores the digital signals corresponding to the digital outputs from the instrument, the digital signals in the scratchpad memory being directed toward the host computer in response to a corresponding instruction by the host computer to the microprocessor means.

14. An interface according to claim 12 wherein the scratchpad memory comprises random access memory (RAM).

15. An interface according to claim 1 wherein digital signals entering the scratchpad memory wraparound once the scratchpad memory is filled.

16. An interface according to claim 1 wherein digital signals entering the scratchpad memory do not wraparound once the scratchpad memory is filled.

17. An interface according to claim 1 wherein digital signals entering the scratchpad memory either (a) wraparound or (b) do not wraparound once the scratchpad memory is filled, the wraparound mode being established by the executive means in response to one corresponding instruction from the host computer and the not wraparound mode being established by the executive means in response to a differing corresponding instruction from the host computer.

18. An interface according to claim 13 wherein digital signals entering the scratchpad memory either (a) wraparound or (b) do not wraparound once the scratchpad memory is filled, the wraparound mode being established by the executive means in response to one corresponding instruction from the host computer and the not wraparound mode being established by the executive means in response to a differing corresponding instruction from the host computer.

19. A interface according to claim 1 wherein each record in the scratchpad memory has an indentifier applied thereto by the microprocessor in response to a corresponding instruction from the host computer.

20. An interface according to claim 18 wherein each record in the scratchpad memory has an identifier applied thereto by the microprocessor in response to a corresponding instruction from the host computer.

21. An interface according to claim 1 wherein the microprocessor points to a record with a particular identifier in response to a corresponding instruction from the host computer.

22. An interface according to claim 1 wherein each of the at least one records has at least one field, and each field has at least one digital character therein;

and

wherein;

(a) the number of records,

(b) the number of fields in each record, and

(c) the number of digital characters in each field

are each determined by the microprocessor in response to a respective instruction from the host computer.

23. An interface according to claim 10 wherein each of the at least one records has at least one field, and each field has at least one digital character therein;

and

wherein;

(a) the number of records,

(b) the number of fields in each record, and

(c) the number of digital characters in each field

are each determined by the microprocessor in response to a respective instruction from the host computer.

24. An interface according to claim 20 wherein each of the at least one records has at least one field, and each field has at least one digital character therein;

and

wherein;

(a) the number of records,

(b) the number of fields in each record, and

(c) the number of digital characters in each field

are each determined by the microprocessor in response to a respective instruction from the host computer.

25. An interface according to claim 1 wherein the microprocessor comprises first handshaking means for directing digital outputs from the host computer back to the host computer for acknowledgement.

26. An interface according to claim 1 wherein the microprocessor means comprises second handshaking means for directing digital outputs from the instrument back to the instrument for accuracy checking.

27. An interface according to claim 25 wherein the microprocessor comprises second handshaking means for directing digital outputs from the instrument back to the instrument for accuracy checking.

34. An interface according to claim 22 wherein in each of the three channels is a full duplex communication channel.

40. A method according to claim 6 wherein the first translator element and the converting means comprise a programmable read-only memory.

41. An interface according to claim 1 further comprising:

means for converting normally prohibited digital data characters from the host computer into digital characters which are required inputs to the instrument.

42. An interface according to claim 5 wherein the converting means changes any digital character which does not correspond to a control character in the instrument into a digital character which corresponds to a required instrument control character.

45. An interface according to claim 10 wherein the deleting means comprise programmable read-only memory (PROM) which is adapted to each distinct instrument coupled to the interface.

46. An interface according to claim 10 wherein the converting means comprise programmable read-only memory (PROM) which is adapted to each distinct instrument coupled to the interface.

47. An interface according to claim 14 wherein the scratchpad memory further comprises an external memory.

48. An interface according to claim 3 wherein the first physical format differs from the standard physical format and the second physical format differs from the standard physical format, and wherein the physical compatibility means comprises:

a first card having a plurality of common types of translator elements thereon and a second card having a plurality of common types of translator elements thereon;

wherein a first translator element selected from the first card is connected between the executive means and the instrument, the first translator element changing the physical format of digital signals communicated to and from the instrument to effect physical compatibility; and

wherein a second translator element selected from the second card is connected between the executive means and the host computer, the second translator element changing the physical format of digital signals communicated to and from the host computer to effect physical compatibility.

28. In a communication system having a digital host computer and an instrument which generates a stream of serial digital outputs to be processed by the host computer, and interface communicatively coupled between the host computer and the instrument, the interface comprising:

a microprocessor having executive means for executing instructions entered one at a time by the host computer into the microprocessor;

means for controlling the timing of communication of the digital outputs to the host computer, the controlling means comprising a scratchpad memory means for storing digital outputs from the instrument in response to a corresponding instruction to the executive means from the host computer, the digital outputs stored in the scratchpad memory means communicated to the host computer in response to a corresponding instruction to the executive means from the host computer; and

means for converting prohibited digital data characters from the instrument into digital characters which are allowed inputs to the host computer.

29. An interface according to claim 28 further comprising:

physical compatibility means for (a) conforming all digital signals entering the interface from the host computer and the instrument into a standard physical format compatible with the microprocessor means and (b) conforming the digital signals exiting the interface into the physical format corresponding to either the host computer or the instrument, respectively, whichever is the destination of the exiting signals.

30. An interface according to claim 28 wherein the microprocessor in response to at least one selectable variable instruction from the host computer, correspondingly selectively divides the scratchpad memory means into a plurality of records and wherein the microprocessor, in response to a corresponding instruction from the host cmputer, directs digital signals, corresponding to the digital outputs from the instrument, into one record after another,

the digital signals thereby being communicated to the host computer in the form of records initially defined by the host computer.

31. In a communication system having a digital host computer, a terminal, and an instrument which generates a stream of serial digital outputs to be processed by the host computer, an interface communicatively coupled between the host computer, the terminal, and the instrument, the interface comprising:

a microprocessor having executive means for executing instructions entered one at a time by the host computer into the microprocessor;

means for controlling the timing of communication of the digital outputs to the host computer in response to a corresponding instruction to the executive means from the host computer, the controlling means comprising a scratchpad memory means for receiving and storing digital signals which correspond to the digital outputs from the instrument, the digital outputs stored in the scratchpad memory means being communicated to the host computer in response to a corresponding instruction to the executive means from the host computer;

physical compatibility means for (a) conforming all digital signals entering the interface from the host computer, the terminal, and the instrument into a standard physical format compatible with the microprocessor means and (b) conforming the digital signals exiting the interface into the physical format corresponding to either the host computer, the terminal, or the instrument, respectively, whichever is the destination of the exiting signals;

means for converting prohibited digital data characters from the instrument into digital characters which are allowed inputs to the host computer; and

means for converting to digital data characters required by the instrument, characters which are normally prohibited to be out from the host computer.

32. An interface according to claim 31 further comprising:

a first communication channel between the host computer and the terminal;

a second communication channel between the host computer and the instrument; and

a third communication channel between the terminal and the instrument;

wherein the executive means opens a selected one of the three channels in response to a corresponding respective instruction from the host computer to the executive means, no more than one channel being open at any time; and

wherein the executive means is transparent to communications between the host computer and the terminal when the first communication channel is open.

33. An interface according to claim 32 wherein the executive means executes a closing of all three channels in response to a corresponding instruction from the host computer to the executive means.

35. An interface according to claim 32 wherein digital signals can be received and stored in the scratchpad memory means in response to the corresponding instruction from the host computer at least substantially simultaneous with communications between the host computer and the terminal when the first channel is open in response to the corresponding instruction from the host computer.

43. An interface according to claim 31 further comprising:

means for converting prohibited digital data characters from the host computer into digital characters which are allowed inputs to the instrument.

36. A method of interfacing by means of a microprocessor (a) an instrument which provides a series of digital outputs and (b) a digital host computer, the method comprising the steps of:

interposing a scratchpad memory between the instrument and the host computer;

forming a set of distinct instructions executable by the microprocessor;

transmitting a first number of the instructions from the host computer to the microprocessor whereupon the microprocessor executes the first number of instructions by dividing the scrathpad memory into a plurality of records;

transmitting a second number of the instructions from the host computer to the microprocessor whereupon the microprocessor executes the second number of instructions by entering digital signals, which correspond to the digital outputs from the instrument, into one record after another; and

transmitting a third number of the instructions from the host computer to the microprocessor whereupon the microprocessor executes the third number of instructions by directing the digital signals entered into the records toward the host computer;

whereby the transmission and execution of the first number of instructions, the second number of instructions, and the third number of instructions in sequence results in the host computer controlling the time at which the host computer is to receive digital inputs corresponding to the digital outputs from the instrument;

the first, second, and third number of instructions each including at least one instruction.

37. A method as in claim 36 wherein the host computer processes digital data in a physical format which differs from the physical format in which the intrument processes, the method comprising the further steps of:

conforming all digital outputs from the host computer and the instrument to a standard physical format;

conforming the digital inputs to the host computer to the physical format compatible therewith; and

conforming the digital inputs to the instrument to the physical format compatible therewith,

thereby avoiding physical incompatibilites between the host computer and the instrument.

38. A method according to claim 36 wherein certain digital characters provided as output by the instrument represent digital characters which the host computer should not receive, the method comprising the further step of;

automatically converting the digital characters which the host computer should not receive into digital characters which are receivable by the host computer,

thereby avoiding coding incompatibilities between the host computer and the instrument.

39. A method according to claim 37 wherein certain digital characters provided as output by the instrument represent digital characters which the host computer should not receive, the method comprising the further step of:

automatically converting the digital characters which the host computer should not receive into digital characters which are receivable by the host computer,

thereby avoiding coding incompatibilities between the host computer and the instrument.

44. A method according to claim 38 comprising the further step of:

automatically converting the digital characters which the host computer normally may not transmit into digital characters which are required by the instrument.