Memory system including RAM and page switchable ROM

• US 4,485,457 A
• Filed: 05/31/1983
• Issued: 11/27/1984
• Est. Priority Date: 05/31/1983
• Status: Expired due to Fees

• Current Assignee: CBS Incorporated (Paramount Global (f/k/a ViacomCBS Inc.))
• Original Assignee: CBS Incorporated (Paramount Global (f/k/a ViacomCBS Inc.))
• Inventors: Hunter, Robert L., Robinson, Scott S. Jr., Balaska, Richard K.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/499,128
• Time in Patent Office: 546 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 463/45
• CPC Class Codes: A63F 13/23 for interfacing with the game device, e.g. specific interfaces between game controller and console
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: G06F 12/0623 for memory modules

Abstract

A memory system for use in a video game system or the like that has a limited number of signal lines for communicating address signals and a data bus, includes random access memory (RAM) to augment that contained in the game console in addition to plural segments of read only memory (ROM). A first decoding circuit is coupled to the data bus and to the signal lines that communicate address signals to the ROM segments, and in response to detection of a predetermined address and a predetermined status of selected data lines produces a signal that selects one of the plurality of ROM segments of memory locations. A second decoding circuit is coupled to a selected group of the address signal lines, and also to a segment of the memory unit set aside for random access memory (RAM) to which the others of the address signal lines are also coupled. When a predetermined address is communicated, the first decoding circuit is inhibited and the second decoding circuit couples an instruction signal to the RAM segment to either write data to or read data from a memory location addressed by the others of the address lines.

Claims

1. For use in a video game system or the like including a game address bus having a limited number of signal lines for conducting address signals, a control bus, and a game data bus, an integratable memory system comprising:

an address bus connectable to the game address bus of the game system for conducting address signals;

a data bus connectable to the game data bus of the game system for conducting data signals;

read only memory means coupled to said address bus and segmented into at least two pages each having a like first plurality of memory locations for providing digital signals on said data bus corresponding to data stored in selected memory locations in response to application thereto of a page select signal unique to the page, the memory locations being selected in response to first address signals on said address bus, and

first decoding means coupled to said address bus and to said data bus for providing the page select signal to a given page of said read only memory means in response to detection of a predetermined combination of first address signals on said address bus and a predetermined combination of data signals on said data bus;

random access memory means coupled to selected ones of the signal lines of said address bus and to said data bus and having a second plurality of memory locations for either accepting digital signals from said data bus or providing digital signals to said data bus corresponding to data stored in selected memory locations in response to the application thereto of either a Write control signal or a Read control signal, respectively, and

second decoding means coupled to the remaining ones of the signal lines of said address bus and to said random access memory means, including means for generating and providing a Write control signal to said random access memory means in response to detecting a first predetermined combination of address signals on the said remaining address lines and providing a Read control signal to said random access memory means in response to detection of a second predetermined combination of address signals on the said remaining address lines, and Write and Read control signals respectively designating whether information is to be written to or read from a memory location of said random access memory means addressed by an address signal on the selected ones of the address lines of said address bus.

2. A memory system according to claim 1, wherein said second decoding means includes means for addressing said random access memory means with twice as many different combinations of address signals on the said selected ones of the address lines of said address bus as there are memory locations in said random access memory means.

3. A memory system according to claim 1, wherein data signals communicated by one selected signal line of said data bus are coupled to said first decoding means.

4. A memory system according to claim 1, wherein said address bus has N signal lines, and

wherein each of the pages of said read only memory means has a number of address locations substantially equal to the remainder resulting from the subtraction of the number of address locations in said random access memory means from the number 2^N.

5. A memory system according to claim 2, wherein said address bus has N signal lines,

wherein said random access memory means has 2⁸ memory locations and has eight signal lines of the said address bus coupled thereto, and

wherein each of the pages of said read only memory means has a number of memory locations substantially equal to the remainder resulting from the subtraction of the number 2⁹ from the number 2^N.

6. A memory system according to claim 1, wherein said first decoding means is normally disabled, and

said second decoding means includes means operative in response to detection of predetermined addresses on the said remaining lines of said address bus for enabling and disabling said first decoding means.

7. For use in a digital system having a system address bus limited to N signal lines for conducting address signals, and a system data bus for conducting data signals, a digital memory system connectable to the said system address and data buses and having a read-only memory (ROM) capacity approximately M times the number of memory locations directly addressable with N address signals, where M is an integer having a value of two or more, and also having random access memory (RAM) capacity, the memory system comprising:

an address bus connectable to the system address bus for conducting address signals,

a data bus connectable to the system data bus for conducting data signals,

a digital memory coupled to said address bus and to said data bus and having approximately 2^N+M memory locations segmented so as to allocate a plurality, R, of the memory locations for utilization as RAM and to provide M pages of read-only memory (ROM) each having a like number of memory locations equal to (2^N -R-M);

first decoding means,

means coupling selected ones of the N signal lines of said address bus to said first decoding means and coupling the balance of the N signal lines to the address circuit of each of the memory locations allocated for RAM, said first decoding means including means for generating and applying to the RAM memory locations one or the other of first and second control signals to respectively designate whether data information is to be written to or read from a selected one of the said RAM memory locations addressed by an address signal on the said selected ones of said N signal lines;

second decoding means coupled to the address bus and to said data bus for detecting communication on said address bus of a predetermined number of said address signals and for detecting communication of data signals on selected lines of said data bus, including output means for providing one of M page select signals in response to detection of communication of the combination of a corresponding one of said predetermined address signals on the address bus and detection of communication of data signals on corresponding ones of selected data lines, and

means coupling the output means of said second decoding means to the memory address circuit of each of the M pages of ROM for communicating the page select signals thereto, the memory address circuit being operable to select a one of the memory locations designated by the combination of address signals conducted on the address bus in the ROM page designated by the page select signal.

8. For a digital system including a system address bus having a limited number of signal lines for conducting address signals, and a system data bus, a memory system having both read only and random access memory capability, the memory system comprising:

a memory means having a plurality, P, of addressable memory locations segmented so as to set aside a selected number, R, of the memory locations for utilization as random access memory (RAM) and to provide a desired number, M, of pages of read-only memory (ROM) each of which has the same number of memory locations, which number is equal to (P-R-M), where M is an integer having a value of two or more,

an address bus connectable to the system address bus and coupled to said memory means for conducting address signals,

a data bus connectable to the system data bus and coupled to said memory means for conducting data signals,

first decoding logic means coupled to said address bus and to said data bus for detecting communication of predetermined ones of said address signals and at least one selected data signal, including means for generating one of M page select signals selected in response to detection of the combination of a corresponding one of said predetermined address signals and at least one selected data signal,

means coupling selected ones of the signal lines of said address bus to the RAM memory locations for communication thereto of predetermined ones of said address signals to designate a one of the plurality of RAM memory locations to which data is to be written or read from, and

second decoding means coupled to those signal lines of the address bus not coupled to the RAM memory locations for detecting communication of predetermined other ones of said address signals, including means for generating and applying to said RAM memory locations either a Read or a Write control signal to respectively designate whether information is to be written to or read from the addressed one of the RAM memory locations.