Data line interface for a time-division multiplexing (TDM) bus

• US 4,485,470 A
• Filed: 06/16/1982
• Issued: 11/27/1984
• Est. Priority Date: 06/16/1982
• Status: Expired due to Term

• Current Assignee: ROLM Systems (Siemens AG)
• Original Assignee: Rolm Corp. (International Business Machines Corporation)
• Inventors: Reali, Peter A.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/388,746
• Time in Patent Office: 895 Days
• Field of Search: 370/100, 370/24, 370/32, 370/85, 370/47, 370/48
• US Class Current: 370/537
• CPC Class Codes: H04L 12/525 involving a stored program control

Abstract

This invention is a data line interface providing a parallel to serial conversion technique for selectively increasing serial data transmission rates. The data line interface receives a 16-bit data word or signal from a TDM bus and transmits it serially to one of a plurality of data terminal interfaces depending on which one is selected. The invention utilizes a double buffer receiver circuit to determine when to speed up the destination transmission clock.

The asynchronous data line interface looks at the value of each of the bits in the data word by sampling the center of each bit. However, during the stop bit, it will not look at the value after sampling the center. Thus, during the time that would have been devoted to the last half of the stop bit, a new start bit may be accepted, allowing the speed up of data to occur.

Claims

1. A system for converting parallel data to serial format for application to a desired destination channel, comprising

bus means for receiving and transferring parallel data, address and command signals, said parallel signals including a stop bit for designating the end of a character;

control means coupled to said bus for receiving the address and command signals from said bus means and generating command signals in response to the signals from said bus means,

first memory means for receiving and storing the data from said bus means in response to a command from said control means,

second memory means for receiving and storing the data from said first memory means,

memory manager means coupled to said first and second memory means for regulating the flow of data from said first memory means to said second memory means in response to a signal from said control means,

bit transmitter means coupled to said second memory means for converting and retiming the parallel data received from said second memory means into a serial format,

bit sampling means for sampling said stop bit, said bit sampling means reading said stop bit during only a portion of said stop bit and causing said memory manager means to begin to input the start of another character to said bit transmitter, thereby allowing said bit transmitter to read said another character after only a portion of said stop bit,

whereby the data from said bus means is converted to serial format and said stop bit is shortened in response to a command from said memory manager means wherein new parallel data can be immediately received from said second memory means such that an overflow of data does not occur.

2. The system of claim 1 further comprising:

a first error detection means for monitoring the first and second memory means to indicate when both of said memories have data contained therein, and also indicating when the first memory means can receive new data;

a second error detecting means coupled to said first and second memory means for indicating an overrun error when new data is received from said bus means when both of said memories have data contained therein, and for providing a means for indicating that the data has a parity error;

and further characterized in that said bit sampling means reads only the first half portion of said stop bit,

whereby said first and second error detector means will provide said error information to said bus means in response to a command from said control means.

3. The system of claim 1 further comprising input means coupled to said bus means for receiving said data signals from said bus means and for transferring said data to said first memory means.

4. The system of claim 2 further comprising output means coupled to said first and second error detecting means for driving said error information into said bus means.

5. The system of claim 1 further comprising:

camp-on means for generating camp-on tones which provide a signal to the desired destination channel to notify the channel that said data will be transmitted thereto, and

mixer means for mixing said camp-on tones with said data from said bit transmitter means,

whereby said mixed data is transmitted to a specific destination channel.

6. The system of claim 1 wherein said control means comprises state clock means for synchronizing said data from said bus means with the output rate of data from said second memory means to said bit transmitter means,

whereby said data rate may be slowed down or speeded up in response to said state clock means.

7. The system of claim 1 further comprising transmitter clock means for controlling the rate at which said bit transmitter means receives the data from said second memory means.

8. The system of claim 3 wherein said input means includes a parity detector means for detecting parity errors in said data from said data bus.

9. A data line interface, for transferring data from a source to a specified destination channel in a data line interface, comprising:

bus for receiving and transferring parallel data characters, and address and command signals, each of said data characters being preceded by a start bit and being ended by a stop bit,

command decoder means coupled to said bus means for receiving address and command signals from said bus means, and generating command signals in response thereto,

input data means coupled to said bus means for receiving said data characters from said bus means,

first memory means coupled to said input data means for receiving and storing said parallel data character from said input data means in response to a command from said control means,

second memory means coupled to said first memory means for receiving and storing said parallel data character from said memory means,

memory manager means coupled to said first and second memory means for regulating the flow of said data character from said first memory means to said second memory means in response to a command from said control means,

bit transmitter means for converting and retiming the parallel data character received from said second memory means into a serial format,

bit sampling means for sampling said stop bit, said bit sampling means reading said stop bit during only a portion of said stop bit and thereafter causing said memory manager means to move the next data character from said second memory means to said bit transmitter for conversion of said next data character into serial format thereby allowing said bit transmitter to read the next data character after only a portion of said stop bit;

first error detecting means for monitoring the first and second memory means to indicate when both of said memories have a data character contained therein, and also indicating when the first memory means can receive a new data character; and

a second error detecting means coupled to said first and second memory means for indicating an overrun error when new data is received from said bus means when both of said memories have data characters stored therein, and for providing a means for indicating that the data has a parity error; and

output buffer means coupled to said first and second error detecting means for driving said error information to said bus means;

whereby the parallel data character from said bus means is converted into serial format and said stop bit is shortened in response to a command from said memory manager means wherein new parallel data can be immediately received from said second memory means such that an overflow of data does not occur.

10. The data line interface of claim 9 further comprising:

camp-on means for generating camp-on tones which provide a signal to a desired destination channel to notify said channel that said data will be transmitted thereto, and

mixer means for mixing said camp-on tones with said data from said bit transmitter means,

whereby said mixed data is transmitted to a specific destination channel.

11. The system of claim 9 wherein said command decoder means comprises a state clock means for synchronizing said data from said bus means with the output rate of data from said second memory means to said bit transmitter means,

whereby said data rate may be slowed down or speeded up in response to said state clock means.

12. The system of claim 9 further comprising transmitter clock means for controlling the rate at which said bit transmitter means receives the data from said second memory means.

13. A system for converting parallel data from a source to serial format for transmission to a specific destination channel, comprising:

bus means for receiving and transferring parallel data, address and command signals, each of said data signals forming a character being preceded by a start bit and being ended by a stop bit;

command control decoder means for receiving the command address and signals from said bus means comprising a state clock means for controlling the flow of said data from said bus means,

first memory means coupled to said command control decoder means, for receiving and storing parallel data from said bus means in response to a command from said control means,

second memory means coupled to said first memory means for receiving and storing the data from said first memory means,

memory manager means coupled to said first and second memory means for regulating the flow of data from said first memory means to said second memory means in response to a signal from said control means, and

bit transmitter means coupled to receive parallel data from said second memory means comprising first means for generating a start bit in response to a command received from said memory manager means, and second means for converting said parallel data into serial data, said first means generating a stop bit at the end of said serial data,

bit sampling means for sampling said stop bit, said bit sampling means reading said stop bit during only a portion of said stop bit and thereafter causing said memory manager means to move the next character from said second memory means to said bit transmitter for conversion of said next character into serial format thereby allowing said bit transmitter to end the next character after only a portion of said stop bit,

whereby said stop bit is shortened in response to a command from said memory manager means wherein new parallel data can be immediately received from said second memory means such that an overflow of data does not occur.

14. The system of claim 13 further comprising:

a first error detection means for monitoring the first and second memory means to indicate when both of said memories have data contained therein, and also indicating when the first memory means can receive new data; and

a second error detecting means coupled to said first and second memory means for indicating an overrun error when new data is received from said bus means before memory space is available in the first or second memory means to store the new data, and for providing a means for indicating that the data has a parity error;

whereby said first and second error detector means will provide said error information to said bus means in response to a command from said control means.

15. The system of claim 13 further comprising output means coupled to said first and second error detecting means for driving said error information into said bus means.

16. The system of claim 13 further comprising:

camp-on means for generating camp-on tones which provide a signal to a desired destination channel to notify said channel that said data will be transmitted thereto, and

mixer means for mixing said camp-on tones with said data from said bit transmitter means,

whereby said mixed data is transmitted to the specific destination channel.

17. The system of claim 13 further comprising transmitter clock means for controlling the rate at which said bit transmitter means receives the data from said second memory means.

18. The system of claim 13 wherein said input means includes a parity detector means for detecting parity errors in said data from said data bus.