Gain switching device with reduced error for watt meter

• US 4,486,707 A
• Filed: 09/24/1982
• Issued: 12/04/1984
• Est. Priority Date: 09/24/1982
• Status: Expired due to Term

• Current Assignee: Schlumbergersema Incorporated
• Original Assignee: Sangamo Weston, Inc.
• Inventors: Randall, Bruce E., Marshall, Jay K.
• Primary Examiner(s): Levy, Stewart J.
• Application Number:
  US06/423,399
• Time in Patent Office: 802 Days
• Field of Search: 324/107, 324/130, 324/142, 328/165, 330/9, 340/347 CC, 364/842
• US Class Current: 324/142
• CPC Class Codes: G01R 15/09 Autoranging circuits
• CPC Class Codes: G01R 21/00 Arrangements for measuring electric power or power factor G01R7/12 takes precedence

Abstract

A gain switching apparatus for a signal is controlled by a switching function formed as a function of the signal. The apparatus is provided with a circuit for reducing errors due to common frequency components in the switching function and in the signal being switched thereby. In order to reduce DC error resulting from multiplication of the switching function by a parameter representing the switched signal, the common frequency component of the switching function is substantially eliminated and replaced by a component at a frequency which is a multiple of the common frequency. A simplified logic circuit is provided to perform the frequency multiplication and the resultant error reduction.

Claims

1. In a switching apparatus for generating a switching function for controlling an input signal having at least a first component of a first frequency, said switching function having an error component at a frequency related to said first frequency,

error reducing means for reducing errors resulting from interaction between said first component of said input signal and said error component of said switching function, said error reducing means comprising:

first means for receiving said error component of said switching function,

second means for receiving another function, and

combining means connected to said first and second means for combining said error component of said switching function and said another function to produce a second switching function having a reduced presence of said error component of said switching function and having a second component of a second frequency having a relationship to said first frequency different from the relationship of said frequency of said error component to said first frequency, said combining means providing said second switching function to said switching means thereby reducing errors due to interaction between said first component of said input signal and said error component of said switching function.

2. An error reducing means as recited in claim 1 wherein the frequency of said error component of said switching function is substantially identical with said first frequency, and further comprising delay means for delaying said error component of said switching function by a predetermined amount and for providing the delayed error component to said second means as said another function.

3. An error reducing means as recited in claim 2 wherein said combining means includes output means for outputting said second switching function to control application of switching means to said input signal.

4. An error reducing means as recited in claim 2 wherein said delay means is operative to delay the error component of said switching function by a submultiple of the period of said first frequency, said combining means including means for replacing said error component of said switching function by a combination of said error component and the delayed error component, thereby providing said second component with a second frequency which is a multiple of said first frequency.

5. An error reducing means as recited in claim 4 including switching means connected for varying gain of a path transmitting a further signal for measurement.

6. An error reducing means as recited in claim 5, the apparatus further comprising analog-to-digital converting means receiving said input signal, and said further signal from said path, for providing digital signals representative thereof.

7. An error reducing means as recited in claim 6, further comprising multiplying means receiving digital signals output from said analog-to-digital converting means and receiving a scaling signal from said output means indicative of the gain provided to said further signal.

8. An error reducing means as recited in claim 7, wherein said analog-to-digital converting means includes input means connected to receive said input signal and said further signal.

9. An error reducing means as recited in claim 8, wherein said input means is connected for receiving voltage and current signals, and

said multiplying means includes output means for providing an indication of power associated with said voltage and current.

10. An error reducing means as recited in claim 1 including generating means generating said switching function responsively to said input signal as a switch control signal at a frequency dependent upon and substantially identical to said first frequency, said generating means connected to provide said switch control signal to said first means,

said error reducing means including a time delay means, having an input connected to receive said switch control signal and an output connected to said second means, for delaying said switch control signal by an amount substantially equal to half the period of said first frequency,

said combining means comprising logic means for combining said switch control signal with the output of said time delay means from said first and second means, respectively, to replace said switch control signal by a substitute switch control signal having a frequency substantially equal to twice said first frequency.

11. An error reducing means as recited in claim 10 wherein said generating means comprises comparator means responsive to said input signal for providing a comparison signal indicative of an instantaneous amplitude thereof.

12. An error reducing means as recited in claim 11 wherein said generating means further comprises latching means for retaining the value of said comparison signal for a controlled period of time and for outputting said switch control signal at said first frequency.

13. An error reducing means as recited in claim 12 wherein said delay means comprises shift register means having a first input for receiving an output of said latching means and a second input for receiving a shifting signal, said shift register means having a predetermined number of stages selected to provide, in conjunction with said synchronizing signal, the delay of one-half the period of said first frequency,

said logic means including logic OR gate means connected to said first and second means for receiving output signals from said holding means and from said shift register means,

whereby said second component of the second switching function incorporates a double frequency repetition of the error component of the switching function at said first frequency as output by the latching means.

14. A gain switching arrangement for providing a plurality of gains to a varying input signal comprising:

(a) first path means for conveying said input signal through a first gain producing circuit and for providing a first gain thereto,

(b) second path means for conveying said input signal through a second circuit having a second gain different from said first gain,

(c) output means,

(d) switching means for selectively switching said input signal through said first or said second path to said output means responsively to a switching signal, and

(e) control means for generating said switching signal and for controlling said switching means to select a specific path for conveying said input signal to said output means,

(f) said control means including

(i) comparing means for comparing an instantaneous value of said input signal with a threshold value and

(ii) signal providing means responsive to said comparing means for providing said switching signal and for causing said first or second paths to be selected by said switching means for conveying said input signal to said output means.

15. An arrangement as recited in claim 14 wherein said first path comprises operational amplifying means with an output for providing said first gain to said input signal, said comparing means being connected to the output of said operational amplifying means for comparing an amplified value of said input signal with said threshold value.

16. An arrangement as recited in claim 14 wherein said control means further comprises latching means for retaining the result of said comparison for a selected period of time and for providing an output representative thereof, and

connecting means for controlling said switching means responsively to said latching means output.

17. An arrangement as recited in claim 16 wherein said signal providing means comprises error reducing means for reducing output errors due to interaction between components having a common frequency, of said input signal and of said output of said latching means.

18. An arrangement as recited in claim 17 wherein said error reducing means comprises delay means for delaying said latching means output by a submultiple of the period of said common frequency and

combining means for combining said latching means output with the delayed latching means output to provide a control signal component for said switching signal at a multiple of said common frequency.

19. An arrangement as recited in claim 18 wherein said delay means comprises shift register means connected to said latching means and providing an output, and said combining means comprises logic

gate means connected to receive the output of said shift register means and the output of said latching means, for providing said control signal at a frequency which is a multiple of said common frequency.

20. An arrangement as recited in claim 19 wherein said shift register means is provided with a predetermined number of stages and with a predetermined clock frequency to store the output of said latching means for one half the period of said common frequency,

whereby said gate means outputs said control signal at double the common frequency.

21. An arrangement as recited in claim 18 further comprising analog-to-digital converting means having output signals,

sample-and-hold means for selectively providing either samples of said input signal from said switching means or samples of a second input signal to said analog-to-digital converting means, and

multiplying means for multiplying the output signals of said analog-to-digital converting means.

22. An arrangement as recited in claim 21 wherein said multiplying means is connected to receive the control signal output by said combining means to determine a scale factor for products produced thereby corresponding to the gain provided to said first mentioned input signal in said first or said second path means.

23. An arrangement as recited in claim 22 further comprising first input means connected for receiving a first signal and for providing that signal to said first or second path means,

second input means for receiving said second input signal,

one of said first and second input means being connected to receive a current input signal and the other being connected to receive a voltage input signal,

one of said first and second input means connected to said first and second path means,

said first and second input means connected to said sample-and-hold means,

said multiplying means providing a product representative of electrical power associated with said voltage and current inputs.