Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
First Claim
1. A method for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream comprising a multiplicity of 8 bit data blocks, said method including partitioning the 8 bit block into two sub-blocks consisting of 5 and 3 contiguous bits, examining each sub-block to determine if any of the individual bits require alteration and altering predetermined bits based on said determination to produce an alternate code pattern, determining the disparity (D0) of the current output sub-block being coded, ascertaining the disparity (D-1) of the last non-zero sub-block coded and selecting a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity in the output code pattern was of a first polarity, assigning the complement of said first code pattern if the last non-zero disparity was of the opposite polarity.
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Abstract
A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.
635 Citations
20 Claims
- 1. A method for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream comprising a multiplicity of 8 bit data blocks, said method including partitioning the 8 bit block into two sub-blocks consisting of 5 and 3 contiguous bits, examining each sub-block to determine if any of the individual bits require alteration and altering predetermined bits based on said determination to produce an alternate code pattern, determining the disparity (D0) of the current output sub-block being coded, ascertaining the disparity (D-1) of the last non-zero sub-block coded and selecting a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity in the output code pattern was of a first polarity, assigning the complement of said first code pattern if the last non-zero disparity was of the opposite polarity.
- 11. A binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, means for testing each input sub-block to determine if any of the individual bits require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (D0) of the current output sub-block being coded, means for determining the disparity (D-1) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said first code pattern if the last non-zero disparity sub-block was of the opposite polarity.
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20. A binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, said partitioning means including means for gating the 3 bit and 5 bit input data sub-blocks into the encoding apparatus for substantially concurrent encoding in separate circuitry provided for each sub-block, means for concatenating an extra bit of a predetermined value at the end of each input data sub-block to form the additional bit of each encoded output sub-block, means for testing each input sub-block to determine if any of the individual bits or the extra bit require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (D0) of the current output sub-block being coded including means for logically combining the input bits of said current input sub-block with the output of the testing and altering means to determine if the disparity of the current sub-block (D0) is zero, positive or negative, means for determining the disparity (D-1) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the input sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said first code pattern if the last non-zero disparity sub-block was of the opposite polarity, said complementing means including means for evaluating all of the input data bits of both sub-blocks and also the polarity (negative or positive) of the last non-zero encoded sub-block.
Specification